參數(shù)資料
型號(hào)： DAC7821IRGPT
廠商： Texas Instruments, Inc.
英文描述： 12-Bit, Parallel Input, Multiplying Digital-to-Analog Converter
中文描述： 12位，并行輸入，乘法數(shù)字到模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 12/18頁(yè)
文件大?。?/td> 1597K
代理商： DAC7821IRGPT
www.ti.com
APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see
Figure 27
), the DAC7821 current output (I
OUT
) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design. For each code change, there is a step function. If the gain bandwidth product (GBP) of the op amp
is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible. Therefore,
for circuit stability, a compensation capacitor C
1
(1 pF to 5 pF typ) can be added to the design, as shown in
Figure 27
.
GND
I
1
OUT
R
FB
V
REF
V
REF
V
DD
V
DD
V
OUT
I
2
OUT
C
1
U1
U2
Positive Voltage Output Circuit
As
Figure 28
illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC7821. This design is suggested instead of using an inverting amp to invert the output as a result of resistor
tolerance errors. For a negative reference, V
OUT
and GND of the reference are level-shifted to a virtual ground
and a –2.5 V input to the DAC7821 with an op amp.
GND
-
2.5V
+2.5VReference
OPA277
GND
I
1
OUT
R
FB
0
V
<
OUT
+2.5V
<
V
OUT
V
REF
V
DD
V
IN
V
DD
V
OUT
I
2
OUT
C
1
OPA277
DAC7821
Bipolar Output Section
The DAC7821, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output I
OUT
is the inverse of the input reference voltage at V
REF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in
Figure 29
,
external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A
4-quadrant multiplying circuit is implemented by using a 2.5 V offset of the reference voltage to bias U4.
According to the circuit transfer equation given in
Equation 2
, input data (D) from code 0 to full-scale produces
output voltages of V
OUT
= –2.5 V to V
OUT
= +2.5 V.
V
OUT
D
0.5
2
N
1
V
REF
(2)
DAC7821
SBAS365A–OCTOBER 2005–REVISED FEBRUARY 2006
Figure 27. Gain Peaking Prevention Circuit with Compensation Capacitor
Figure 28. Positive Voltage Output Circuit
12
相關(guān)PDF資料
PDF描述
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