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參數(shù)資料
| 型號： | DAC8012JU-BI |
| 英文描述： | 12-Bit Digital-to-Analog Converter |
| 中文描述： | 12位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 211K |
| 代理商： | DAC8012JU-BI |
6
DAC80/80P
(pin 16) for specified operation. This reference may be used
externally also, but external current drain is limited to
2.5mA.
If a varying load is to be driven, an external buffer amplifier
is recommended to drive the load in order to isolate bipolar
offset from load variations. Gain and bipolar offset adjust-
ments should be made under constant load conditions.
LOGIC INPUT COMPATIBILITY
DAC80 digital inputs are TTL, LSTTL and 4000B,
54/74HC CMOS compatible. The input switching threshold
remains at the TTL threshold over the entire supply range.
Logic “0” input current over temperature is low enough to
permit driving DAC80 directly from outputs of 4000B and
54/74C CMOS devices.
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
Connect power supply voltages as shown in Figure 3. For
optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown. These
capacitors (1
μ
F tantalum) should be located close to the
DAC80.
±
12V OPERATION
All DAC80 models can operate over the entire power supply
range of
±
11.4V to
±
16.5V. Even with supply levels drop-
ping to
±
11.4V, the DAC80 can swing a full
±
10V range,
provided the load current is limited to
±
2.5mA. With power
supplies greater than
±
12V, the DAC80 output can be loaded
up to
±
5mA. For output swing of
±
5V or less, the output
current is
±
5mA, minimum, over the entire V
CC
range.
No bleed resistor is needed from +V
CC
to pin 24, as was
needed with prior hybrid Z versions of DAC80. Existing
±
12V applications that are being converted to the monolithic
DAC80 must omit the resistor to pin 24 to insure proper
operation.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by installing external Offset
and Gain potentiometers. Connect these potentiometers as
shown in Figure 3 and adjust as described below. TCR of the
potentiometers should be 100ppm/
°
C or less. The 3.9M
and 10M
resistors (20% carbon or better) should be lo-
cated close to the DAC80 to prevent noise pickup. If it is not
convenient to use these high value resistors, an equivalent
“T” network, as shown in Figure 4, may be substituted.
FIGURE 2. Power Supply Rejection vs Power Supply Ripple.
FIGURE 3. Power Supply and External Adjustment Connection Diagrams.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Reference
Control
Circuit
12-Bit
Resistor
Ladder
Network
and
Current
Switches
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Reference
Control
Circuit
12-Bit
Resistor
Ladder
Network
and
Current
Switches
Voltage Output Models
Current Output Models
5k
5k
6.3k
2k
3k
6.3k
5k
3.9M
1μF
0.01μF
10k
to
100k
10k
to
100k
+V
CC
–V
CC
+V
CC
–V
CC
10M
3.9M
0.01μF
10k
to
100k
10k
to
100k
+V
CC
–V
CC
+V
CC
–V
CC
10M
1μF
1μF
1μF
1
10
100
1k
10k
100k
0.1
0.01
0.001
0.0001
Power Supply Ripple Frequency (Hz)
%
C
+V
CC
–V
CC
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