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參數(shù)資料
| 型號(hào)： | DAC8248FS-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL W/BUFF 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 1µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 1M |
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DAC8248
–12–
REV. B
INTERFACE CONTROL LOGIC PIN FUNCTIONS
LSB
/MSB – (PIN 17) LEAST SIGNIFICANT BIT (Active
Low)/ MOST SIGNIFICANT BIT (Active High). Selects
lower 8-bits (LSBs) or upper 4-bits (MSBs); either can be
loaded first. It is used with the WR signal to load data into the
input registers. Data is loaded in a right justified format.
DAC A
/DAC B – (PIN 18) DAC SELECTION. Active low
for DAC A and Active High for DAC B.
WR
– (PIN 20) WRITE – Active Low. Used with the LSB/
MSB signal to load data into the input registers, or Active High
to latch data into the input registers.
LDAC
– (PIN 19) LOAD DAC. Used to transfer data sim-
ultaneously from DAC A and DAC B input registers to both
DAC output registers. The DAC register becomes transparent
(activity on the digital inputs appear at the analog output) when
both WR and LDAC are low. Data is latched into the output
registers on the rising edge of LDAC.
RESET
– (PIN 16) – Active Low. Functions as a zero over-
ride; all registers are forced to zero when the RESET signal is
low. All registers are latched to zeros when the write signal is
high and RESET goes high.
APPLICATIONS INFORMATION
UNIPOLAR OPERATION
Figure 7 shows a simple unipolar (2-quadrant multiplication)
circuit using the DAC8248 and OP270 dual op amp (use two
OP42s for applications requiring higher speeds), and Table I
shows the corresponding code table. Resistors R1, R2, and R3,
R4 are used only if full-scale gain adjustments are required.
Table I. Unipolar Binary Code Table (Refer to Figure 7)
Binary Number in
DAC Register
Analog Output, VOUT
MSB
LSB
(DAC A or DAC B)
1111 1111 1111
–VREF
4095
4096
1000 0000 0000
–VREF
2048
4096
= –
1
2
VREF
0000 0000 0001
–VREF
1
4096
0000 0000 0000
0 V
NOTE
1 LSB = (2
-12) (V
REF)=
1
4096
(VREF)
Figure 7. Unipolar Configuration (2-Ouadrant Multiplication)
Low temperature-coefficient (approximately 50 ppm/
°C) resis-
tors or trimmers should be used. Maximum full-scale error
without these resistors for the top grade device and VREF =
±10 V is 0.024%, and 0.049% for the low grade. Capacitors C1
and C2 provide phase compensation to reduce overshoot and
ringing when high-speed op amps are used.
Full-scale adjustment is achieved by loading the appropriate
DAC’s digital inputs with 1111 1111 1111 and adjusting R1 (or
R3 for DAC B) so that:
VOUT = VREF ×
4095
4096
Full-scale can also be adjusted by varying VREF voltage and
eliminating R1, R2, R3, and R4. Zero adjustment is performed by
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| DAC8248FSZ | 功能描述:IC DAC 12BIT DUAL W/BUFF 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| DAC8248FSZ-REEL | 功能描述:IC DAC 12BIT DUAL W/BUFF 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| DAC8248FW | 制造商:Analog Devices 功能描述: |
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