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參數(shù)資料
型號: DAC8412FPZ
廠商: Analog Devices Inc
文件頁數(shù): 16/20頁
文件大?。?/td> 0K
描述: IC DAC 12BIT QUAD W/READBK 28DIP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: DAC8412/3 Redesign and Fab Process Change 01/Oct/2009
標(biāo)準(zhǔn)包裝: 13
設(shè)置時間: 6µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
功率耗散(最大): 330mW
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 28-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 28-PDIP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 167k
Data Sheet
DAC8412/DAC8413
Rev. G | Page 5 of 20
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Write Data Setup
tWDS
tWCS = 150 ns
20
ns
Write Data Hold
tWDH
tWCS = 150 ns
0
ns
Load Data Pulse Width
tLDW
180
ns
Reset Pulse Width
tRESET
150
ns
Chip Select Read Pulse Width
tRCS
170
ns
Read Data Hold
tRDH
tRCS = 170 ns
20
ns
Read Data Setup
tRDS
tRCS = 170 ns
0
ns
Data to High-Z
tDZ
CL = 10 pF
200
ns
Chip Select to Data
tCSD
CL = 100 pF
320
ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
PSS
100
ppm/V
Positive Supply Current
IDD
7
12
mA
Negative Supply Current
ISS
VSS = 5.0 V
10
mA
Power Dissipation
PDISS
VSS = 0 V
60
mW
VSS = 5.0 V
110
mW
1 All supplies can be varied ±5%, and operation is guaranteed. Device is tested with VDD = 4.75 V.
2 For single-supply operation only (VREFL = 0.0 V, VSS = 0.0 V). Due to internal offset errors, INL and DNL are measured beginning at 0x005.
3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4 All parameters are guaranteed by design.
5 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
CS
A0/A1
tRDS
tRCS
tRDH
tAS
tAH
tDZ
tCSD
R/W
DATA
OUT
DATA VALID
HIGH-Z
00
27
4-
00
3
Figure 3. Data Output (Read Timing)
A0/A1
RESET
LDAC
tWCS
R/W
CS
DATA IN
tWS
tWH
tAS
tAH
tLS
tLH
tWDH
tWDS
tLDW
tRESET
00
27
4-
0
04
Figure 4. Data Write (Input and Output Registers) Timing
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