參數(shù)資料
型號(hào): DAC8413EP
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: Quad, 12-Bit DAC Voltage Output with Readback
中文描述: QUAD, PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PDIP28
封裝: PLASTIC, MS-001, DIP-28
文件頁(yè)數(shù): 4/14頁(yè)
文件大小: 443K
代理商: DAC8413EP
DAC8412/DAC8413
–4–
REV. D
CS
R/
W
A0/A1
DATA
OUT
DATA
VALID
t
DZ
HI-Z
HI
-Z
t
RCS
t
RDS
t
RDH
t
AS
t
AH
t
CSD
Figure 2. Data Output (Read Timing)
CS
R/
W
A0/A1
DATA
IN
t
WCS
RESET
t
WS
t
WH
t
AH
t
AS
t
LS
t
WDS
t
WDH
t
LDW
t
RESET
LDAC
t
LH
Figure 3. Data WRITE (Input and Output Registers) Timing
CS
R/
W
ADDRESS
LDAC
DATA
IN
80ns
t
WS
t
AS
t
LS
t
WDS
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
t
WDH
t
LH
t
WH
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
Figure 4. Single Buffer Mode
CS
R/
W
ADDRESS
LDAC
DATA
IN
80ns
t
WS
t
AS
t
LS
t
WDS
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
t
WDH
t
LH
t
WH
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
t
LDW
Figure 5. Double Buffer Mode
C1
C1
D1
C2
C1
D1
D1
R2
R1
R2
N/C
N/C C2
C2
R3
R3
N/C
N/C
C2
V
DD
V
REFH
V
REFL
+
+
+
R4
R4
R6
R1
DGND
V
SS
D1
C1
+
V
REFH
V
OUTB
V
OUTA
V
SS
DGND
RESET
LDAC
V
REFL
V
OUTC
V
OUTD
V
DD
V
LOGIC
CS
A0
A1
R/
W
DB11
DB10
DB9
DB8
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
*
V
DD
=
+15V,
V
SS
=
15V,
V
REFH
=
+10V,
V
REFL
=
0V
R1
=
10 ,
R2
=
100 ,
R3
=
5k ,
R4
= 10k , R5 = 100k ,
R6 = 47 FOR LCC, R6 = 100 FOR DIP
C1 = 4.7 F (ONCE PER PORT), C2 = 0.01 F (EACH DEVICE)
D1 = 1N4001 OR EQUIVALENT (ONCE PER PORT)
ONCE
PER
PORT
R5
R3
Figure 6. Burn-In Diagram
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