DAC8420
Rev. B | Page 3 of 24
SPECIFICATIONS
@ VDD = +5.0 V ± 5%, VSS = 0 V, VVREFHI = +2.5 V, VVREFLD = 0 V, and VSS = 5.0 V ± 5%, VVREFLO = 2.5 V, 40°C ≤ TA ≤ +85°C unless
Table 1.
Parameter
Symbol
Condition
Min
Typ
Max
Unit
STATIC ACCURACY
Integral Linearity E Grade
INL
±
±1
LSB
Integral Linearity E Grade
INL
±
±3
LSB
Integral Linearity F Grade
INL
±
±2
LSB
Integral Linearity F Grade
INL
±1
±4
LSB
Differential Linearity
DNL
Monotonic over temperature
±
±1
LSB
Zero-Scale Error
ZSE
RL = 2 kΩ, VSS = 5 V
±4
LSB
Full-Scale Error
FSE
RL = 2 kΩ, VSS = 5 V
±4
LSB
Zero-Scale Error
ZSE
±8
LSB
Full-Scale Error
FSE
±8
LSB
Zero-Scale Temperature Coefficient
TCZSE
±10
ppm/°C
Full-Scale Temperature Coefficient
TCFSE
±10
ppm/°C
MATCHING PERFORMANCE
Linearity Matching
±1
LSB
REFERENCE
Positive Reference Input Ra
nge5VVREFHI
VVREFLO + 2.5
VDD 2.5
V
Negative Reference Input Rang
e5VVREFLO
VSS
VVREFHI 2.5
V
Negative Reference Input Range
VVREFLO
0
VVREFHI 2.5
V
Reference High Input Current
IVREFHI
Code 0x000, Code 0x555
0.75
±0.25
+0.75
mA
Reference Low Input Current
IVREFLO
Code 0x000, Code 0x555, VSS = 5 V
1.0
0.6
mA
AMPLIFIER CHARACTERISTICS
Output Current
IOUT
VSS = 5 V
1.25
+1.25
mA
Settling Time
tS
8
μs
Slew Rate
SR
1.5
V/μs
LOGIC CHARACTERISTICS
Logic Input High Voltage
VINH
2.4
V
Logic Input Low Voltage
VINL
0.8
V
Logic Input Current
IIN
10
μA
CIN
13
pF
LOGIC TIMING CHARACTERISTIC
S4, 7Data Setup Time
tDS
25
ns
Data Hold
tDH
55
ns
Clock Pulse Width High
tCH
90
ns
Clock Pulse Width Low
tCL
120
ns
Select Time
tCSS
90
ns
Deselect Delay
tCSH
5
ns
Load Disable Time
tLD1
130
ns
Load Delay
tLD2
35
ns
Load Pulse Width
tLDW
80
ns
Clear Pulse Width
tCLRW
150
ns