參數(shù)資料
型號(hào)： DAC8426FR
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Quad 8-Bit Voltage Out CMOS DAC Complete with Internal 10 V Reference
中文描述： QUAD, PARALLEL, 8 BITS INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, CDIP20
封裝： CERDIP-20
文件頁數(shù)： 4/12頁
文件大小： 289K
代理商： DAC8426FR
DAC8426
–4–
REV. C
DICE CHARACT E RIST ICS
DIE SIZE 0.129
×
0.152 inch, 19,608 sq. mils
(3.28
×
3.86 mm, 12.65 sq. mm)
1. V
OUT B
2. V
OUT A
3. V
SS
4. V
REF
OUT
5. AGND
6. DGND
7. DB
7
(MSB)
8. DB
6
9. DB
5
10. DB
4
11. DB
3
12. DB
2
13. DB
1
14. DB
0
(LSB)
15.
WR
16. A
1
17. A
0
18. V
DD
19. V
OUT D
20. V
OUT C
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8426 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
DAC8426GBC
Limits
Parameter
Symbol
Conditions
Units
T otal Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Zero Code Error
DAC Output Current
Reference Output Voltage
Load Regulation
Line Regulation
Reference Output Current
Logic Inputs High
Logic Inputs Low
Logic Input Current
Positive Supply Current
Negative Supply Current
T UE
INL
DNL
G
FSE
V
ZSE
I
OUT
SOURCE
V
REF
OUT
LD
REG
LN
REG
I
REF
OUT
V
INH
V
INL
I
IN
I
DD
I
SS
±
2
±
1
±
1
±
1
±
20
10
10.04
0.1
0.04
5
2.4
0.8
±
1
14
10
LSB max
LSB max
LSB max
LSB max
mV max
mA min
V max
%/mA max
%/V max
mA min
V min
V max
μ
A max
mA max
mA max
Digital In = All Ones
No Load
I
L
= 5 mA
V
DD
=
±
10 V
V
REF
OUT < 40 mV
V
IN
= 0 V or V
DD
V
IN
= V
INL
or V
INH
V
IN
= V
INL
or V
INH’
V
SS
= –5 V
NOT E
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
WAFER TEST LIMTS
at V
DD
= +15 V
6
5%; V
SS
= AGND = DGND = 0 V; unless otherwse specified. T
A
= +25
8
C. All specifications
apply for DACs A, B, C, and D.
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