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| 型號(hào)： | DAC8426FR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Quad 8-Bit Voltage Out CMOS DAC Complete with Internal 10 V Reference |
| 中文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 289K |
| 代理商： | DAC8426FR |
DAC8426
–7–
REV. C
PARAME T E R DE FINIT IONS
T OT AL UNADJUST E D E RROR (T UE )
T his specification includes the Full-Scale-Error, Relative Accu-
racy Zero-Code-Error and the internal reference voltage. T he
ideal Full-Scale output voltage is 10 V minus 1 LSB which
equals 9.961 volts. Each LSB equals 10 V
×
(1/256) = 0.039 volts.
DIGIT AL CROSST ALK
Digital crosstalk is the signal coupled to the output of a DAC
due to a changing digital input from adjacent DACs being up-
dated. It is specified in nano-Volt-seconds (nVs).
CIRCUIT DE SCRIPT ION
T he DAC8426 is a complete quad 8-bit D/A converter. It con-
tains an internal bandgap reference, four voltage switched R-2R
ladder DACs, four DAC latches, four output buffer amplifiers,
and an address decoder. All four DACs share the internal ten
volt reference and analog ground(AGND). Figure 1 provides an
equivalent DAC plus buffer schematic.
Figure 1. Simplified Circuit Configuration for One DAC.
(Switches Are Shown for All “ 1s” on the Digital Inputs.)
T he eleven digital inputs are compatible with both T T L and 5 V
(or higher) CMOS logic. T able I shows the DAC control logic
truth table for
WR
, A
1
, and A
0
operation. When
WR
is active
low the input latch of the selected DAC is transparent, and the
DAC’s output responds to the data present on the eight digital
data inputs (DBx). T he data (DBx) is latched into the ad-
dressed DAC’s latch on the positive edge of the
WR
control sig-
nal. T he important timing requirements are shown in the Write
Cycle T iming Diagram, Figure 2.
INT E RNAL 10 VOLT RE FE RE NCE
T he internal 10 V bandgap reference of the DAC8426 is trimm-
ed to the output voltage and temperature drift specifications.
T his internal reference is connected to the reference inputs of
the four internal 8-bit D/A converters. T he output terminal of
the internal 10 V reference is available on pin 4. T he 10 V out-
put of the reference is produced with respect to the AGND pin.
T his reference output can be used to supply as much as 5 mA of
additional current to external devices. Care has been taken in
T able I. DAC Control Logic T ruth T able
Logic Control
WR
A
1
DAC8426
Operation
A
0
H
X
X
No Operation
Device Not Selected
DAC A T ransparent
DAC A Latched
DAC B T ransparent
DAC B Latched
DAC C T ransparent
DAC C Latched
DAC D T ransparent
DAC D Latched
L
g
L
g
L
g
L
g
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L = Low State, H = High State, X = Don’t Care
Figure 2. Write Cycle Timing Diagram
the design of the internal DAC switching to minimize transients
on the reference voltage terminal (V
REF
OUT ). Other devices
connected to this reference terminal should have well behaved
input loading characteristics. D/A converters such as the PMI
PM7226A have been designed to minimize reference input tran-
sient currents and can be directly connected to the DAC8426
10 V reference. Devices exhibiting large current transients due
to internal switching should be buffered with an op amp to
maintain good overall system noise performance. A 10
μ
F refer-
ence output bypass capacitor is required.
BUFFE R AMPLIFIE R SE CT ION
T he four internal unity-gain voltage buffers provide low output
impedance capable of sourcing 5 mA or sinking 350
μ
A. T ypical
output slew rates of
±
4 V/
μ
s are achieved with 10 V full-scale out-
put changes and R
L
= 2 k
. Figure 3 photographs show large sig-
nal and settling time response. Capacitive loads to 3300 pF
maximum, and resistive loads to 2 k
minimum can be applied.
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