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參數(shù)資料
| 型號(hào)： | DAC8532 |
| 英文描述： | Dual Channel, Low Power, 16-Bit, Serial Input DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 雙通道，低功耗，16位，串行輸入數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 402K |
| 代理商： | DAC8532 |
11
DAC8532
SBAS246A
www.ti.com
INPUT SHIFT REGISTER
The input shift register of the DAC8532 is 24 bits wide (see
Figure 5) and is made up of 8 control bits (DB16-DB23) and 16
data bits (DB0-DB15). The first two control bits (DB22 and
DB23) are reserved and must be
“
0
”
for proper operation. LD
A (DB20) and LD B (DB21) control the updating of each analog
output with the specified 16-bit data value or power-down
command. Bit DB19 is a
“
Don't Care
”
bit which does not affect
the operation of the DAC8532 and can be 1 or 0. The following
control bit, Buffer Select (DB18), controls the destination of the
data (or power-down command) between DAC A and DAC B.
The final two control bits, PD0 (DB16) and PD1 (DB17), select
the power-down mode of one or both of the DAC channels. The
four modes are normal mode or any one of three power-down
modes. A more complete description of the operational modes
of the DAC8532 can be found in the Power-Down Modes
section. The remaining sixteen bits of the 24-bit input word
make up the data bits. These are transferred to the specified
Data Buffer or DAC Register, depending on the command
issued by the control byte, on the 24th falling edge of SCLK.
Please refer to Tables II and III for more information.
are set to zero-scale; they remain there until a valid write
sequence and load command is made to the respective
DAC channel. This is useful in applications where it is
important to know the state of the output of each DAC
output while the device is in the process of powering up.
No device pin should be brought high before power is
applied to the device.
POWER-DOWN MODES
The DAC8532 utilizes four modes of operation. These modes
are accessed by setting two bits (PD1 and PD0) in the control
register and performing a
“
Load
”
action to one or both DACs.
Table I shows how the state of the bits correspond to the
mode of operation of each channel of the device. (Each DAC
channel can be powered down simultaneously or indepen-
dently of each other. Power-down occurs after proper data is
written into PD0 and PD1 and a
“
Load
”
command occurs.)
Please refer to the "Operation Examples" section for addi-
tional information.
Resistor
String DAC
Amplifier
Power-down
Circuitry
Resistor
Network
V
OUT
X
FIGURE 3. Output Stage During Power-Down (High-Impedance)
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept LOW for
at least 24 falling edges of SCLK and the addressed DAC
register is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge, it acts as
an interrupt to the write sequence; the shift register is reset
and the write sequence is discarded. Neither an update of
the data buffer contents, DAC register contents or a change
in the operating mode occurs (see Figure 4).
POWER-ON RESET
The DAC8532 contains a power-on reset circuit that con-
trols the output voltage during power-up. On power-up, the
DAC registers are filled with zeros and the output voltages
PD1 (DB17)
PD0 (DB16)
OPERATING MODE
0
—
0
1
1
0
—
1
0
1
Normal Operation
Power-Down Modes
Output Typically 1k
to GND
Output Typically 100k
to GND
High Impedance
TABLE I. Modes of Operation for the DAC8532.
When both bits are set to 0, the device works normally with
a typical power consumption of 500
μ
A at 5V. For the three
power-down modes, however, the supply current falls to
200nA at 5V (50nA at 3V). Not only does the supply current
fall but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the
device is known while it is in power-down mode. There are
three different options for power-down: The output is con-
nected internally to GND through a 1k
resistor, a 100k
resistor, or it is left open-circuited (High-Impedance). The
output stage is illustrated in Figure 3.
All analog circuitry is shut down when the power-down mode
is activated. Each DAC will exit power-down when PD0 and
PD1 are set to 0, new data is written to the Data Buffer, and
the DAC channel receives a
“
Load
”
command. The time to
exit power-down is typically 2.5
μ
s for V
DD
= 5V and 5
μ
s for
V
DD
= 3V (See the Typical Characteristics).
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