參數(shù)資料
型號(hào): DAC8532IDGK
英文描述: Dual Channel, Low Power, 16-Bit, Serial Input DIGITAL-TO-ANALOG CONVERTER
中文描述: 雙通道,低功耗,16位,串行輸入數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù): 10/19頁
文件大?。?/td> 402K
代理商: DAC8532IDGK
DAC8532
SBAS246A
10
www.ti.com
THEORY OF OPERATION
DAC SECTION
The architecture of each channel of the DAC8532 consists of
a resistor string DAC followed by an output buffer amplifier.
Figure 1 shows a simplified block diagram of the DAC
architecture.
The input coding for each device is unipolar straight binary,
so the ideal output voltage is given by:
V
X
V
D
OUT
REF
=
65536
where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
V
OUT
X refers to channel A or B.
RESISTOR STRING
The resistor string section is shown in Figure 2. It is simply
a divide-by-2 resistor followed by a string of resistors, each
of value R. The code loaded into the DAC register deter-
mines at which node on the string the voltage is tapped off.
This voltage is then applied to the output amplifier by closing
one of the switches connecting the string to the amplifier.
OUTPUT AMPLIFIER
Each output buffer amplifier is capable of generating rail-to-
rail voltages on its output which approaches an output range
of 0V to V
DD
(gain and offset errors must be taken into
account). Each buffer is capable of driving a load of 2k
in
parallel with 1000pF to GND. The source and sink capabili-
ties of the output amplifier can be seen in the typical charac-
teristics.
SERIAL INTERFACE
The DAC8532 uses a 3-wire serial interface (SYNC, SCLK,
and D
IN
), which is compatible with SPI
, QSPI
, and
Microwire
interface standards, as well as most DSPs. See
the Serial Write Operation timing diagram for an example of
a typical write sequence.
SPI and QSP are registered trademarks of Motorola.
Microwire is a registered trademark of National Semiconductor.
DAC Register
REF (+)
Resistor String
REF(
)
Output
Amplifier
GND
V
REF
V
OUT
X
FIGURE 1. DAC8532 Architecture.
To Output
Amplifier
(2x Gain)
R
R
R
R
V
REF
2
V
REF
R
DIVIDER
FIGURE 2. Resistor String.
The write sequence begins by bringing the SYNC line LOW.
Data from the D
IN
line is clocked into the 24-bit shift register
on each falling edge of SCLK. The serial clock frequency can
be as high as 30MHz, making the DAC8532 compatible with
high speed DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked into the shift register and the
programmed function is executed (i.e., a change in Data
Buffer contents, DAC Register contents, and/or a change in
the power-down mode of a specified channel or channels).
At this point, the SYNC line may be kept LOW or brought
HIGH. In either case, the minimum delay time from the 24th
falling SCLK edge to the next falling SYNC edge must be met
in order to properly begin the next cycle. To assure the
lowest power consumption of the device, care should be
taken that the digital input levels are as close to each rail as
possible. (Please refer to the
Typical Characteristics
sec-
tion for the
Supply Current vs Logic Input Voltage
transfer
characteristic curve).
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