參數(shù)資料
型號(hào): DAC8551IDGK
廠商: Texas Instruments, Inc.
英文描述: 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER
中文描述: 16位,超低毛刺電壓輸出數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 15/22頁(yè)
文件大?。?/td> 1740K
代理商: DAC8551IDGK
www.ti.com
INPUT SHIFT REGISTER
The input shift register is 24 bits wide, as shown in
Figure 49
. The first six bits are
don't cares
. The next
two bits (PD1 andPD0) are control bits that control
which mode of operation the part is in (normal mode
or any one of three power-down modes). A more
complete description of the various modes is located
in the Power-Down Modes section. The next 16 bits
are the data bits. These are transferred to the DAC
register on the 24th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
DAC is updated on the 24th falling edge. However, if
SYNC is brought HIGH before the 24th falling edge, it
acts as an interrupt to the write sequence. The shift
register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register con-
tents, or a change in the operating mode occurs, as
shown in
Figure 50
.
POWER-ON RESET
The DAC8551 contains a power-on-reset circuit that
controls the output voltage during power up. On
power up, the DAC registers is filled with zeros and
the output voltages is 0 V; it remains there until a
valid write sequence is made to the DAC. This is
useful in applications where it is important to know
the state of the output of the DAC while it is in the
process of powering up.
CLK
SYNC
D
IN
Valid Write Sequence: Output Updates
on the 24th Falling Edge
24th Falling Edge
24th Falling Edge
DB23
DB80
DB23
DB80
DAC8551
SLAS429A–APRIL 2005–REVISED JULY 2005
DB23
DB0
X
X
X
X
X
X
PD1
PD0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 49. DAC8551 Data Input Register Format
Figure 50. SYNC Interrupt Facility
15
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