參數(shù)資料
型號: DAC8551IDGK
廠商: Texas Instruments, Inc.
英文描述: 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER
中文描述: 16位,超低毛刺電壓輸出數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 5/22頁
文件大?。?/td> 1740K
代理商: DAC8551IDGK
www.ti.com
TIMING REQUIREMENTS
(1)(2)
V
DD
= 2.7 V to 5.5 V, all specifications –40
°
C to 105
°
C (unless otherwise noted)
SERIAL WRITE OPERATION
SCLK
SYNC
D
IN
DB23
DB0
t
8
t
3
t
2
t
7
t
4
t
5
t
6
t
1
DAC8551
SLAS429A–APRIL 2005–REVISED JULY 2005
PARAMETER
TEST CONDITIONS
MIN
50
33
13
13
22.5
13
TYP
MAX
UNIT
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
t
1(3)
SCLK cycle time
ns
t
2
SCLK HIGH time
ns
t
3
SCLK LOW time
ns
0
0
5
5
t
4
SYNC to SCLK rising edge setup time
ns
t
5
Data setup time
ns
4.5
4.5
t
6
Data hold time
ns
0
0
t
7
SCLK falling edge to SYNC rising edge
ns
50
33
t
8
Minimum SYNC HIGH time
ns
(1)
(2)
(3)
All input signals are specified with t
= t
= 3 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See Serial Write Operation timing diagram.
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V and 20 MHz at V
DD
= 2.7 V to 3.6 V.
5
相關(guān)PDF資料
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