參數(shù)資料
型號(hào): DAC8551IDRBR
廠商: Texas Instruments, Inc.
英文描述: 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER
中文描述: 16位,超低毛刺電壓輸出數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù): 12/22頁
文件大小: 1740K
代理商: DAC8551IDRBR
www.ti.com
100
300
500
700
0
0.5
1
1.5
2
2.5
D
I
S
A
μ
V
DD
= V
REF
= 2.7 V
T
A
= 25
°
C, SCL Input (All Other Inputs = GND)
V
(LOGIC)
V
0
50
100
150
200
250
40
10
20
50
80
110
Q
μ
Temperature C
V
DD
= V
REF
= 2.7 V
Reference Current Included
Time (2
μ
s/div)
V
DD
= 2.7 V,
V
= 2.5 V,
From Code: 0000
Zoomed Rising Edge
1 mV/div
Trigger Pulse
Rising
Edge
0.5 V/div
V
DD
= 2.5 V,
V
From Code: FFFF
To Code: 0000
Zoomed Falling Edge
1 mV/div
Trigger Pulse
2.7 V/div
Falling
0.5 V/div
Time (2
μ
s/div)
Trigger Pulse
2.7 V/div
Zoomed Rising Edge
1 mV / div
V
DD
= 2.7 V
V
REF
= 2.5 V
From code; 4000
To code: CFFF
Rising
Edge
0.5 V/div
Time 2 s/div
V
DD
= 2.7 V,
V
= 2.5 V,
From Code: CFFF
To Code: 4000
Zoomed Falling Edge
1 mV/div
Trigger Pulse
2.7 V/div
Falling
Edge
Time (2
μ
s/div)
DAC8551
SLAS429A–APRIL 2005–REVISED JULY 2005
TYPICAL CHARACTERISTICS: V
DD
= 2.7 V (continued)
At T
A
= 25
°
C, unless otherwise noted
POWER-SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
Figure 35.
Figure 36.
FULL-SCALE SETTLING TIME: 2.7-V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Figure 37.
Figure 38.
HALF-SCALE SETTLING TIME: 2.7-V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7-V FALLING EDGE
Figure 39.
Figure 40.
12
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