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參數(shù)資料
| 型號(hào)： | DAC8562FP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +5 Volt, Parallel Input Complete 12-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大?。?/td> | 636K |
| 代理商： | DAC8562FP |
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DAC8562
REV. A
–10–
15
16
DGND
10
AGND
12
DATA
DAC-8562
13
V
OUT
+12V OR +15V
CE
CLR
1
0.1μF
4
REF-02
6
2
0.1μF
Figure 31. Operating the DAC8562 on +12 V or +15 V
Supplies Using a REF02 Voltage Reference
Measuring Offset Error
One of the most commonly specified endpoint errors associated
with real-world nonideal DACs is offset error.
In most DAC testing, the offset error is measured by applying
the zero-scale code and measuring the output deviation from
0 volt. There are some DACs where offset errors may be present
but not observable at the zero scale because of other circuit limi-
tations (for example, zero coinciding with single supply ground).
In these DACs, nonzero output at zero code cannot be read as
the offset error. In the DAC8562, for example, the zero-scale er-
ror is specified to be +3 LSBs. Since zero scale coincides with
zero volt, it is not possible to measure negative offset error.
By adding a pull-down resistor from the output of the
DAC8562 to a negative supply as shown in Figure 32, offset er-
rors can now be read at zero code. This configuration forces the
output P-channel MOSFET to source current to the negative
supply thereby allowing the designer to determine in which di-
rection the offset error appears. The value of the resistor should
be such that, at zero code, current through the resistor is 200
μ
A
maximum.
15
16
DGND
10
AGND
12
V
DD
DATA
DAC-8562
13
0.1μF
V
OUT
+5V
CE
CLR
20
200μA MAX
V–
Figure 32. Measuring Zero-Scale or Offset Error
Unipolar Output Operation
This is the basic mode of operation for the DAC8562. As shown
in Figure 30, the DAC8562 has been designed to drive loads as
low as 820
in parallel with 500 pF. The code table for this op-
eration is shown in Table III.
15
16
DGND
10
AGND
12
V
DD
DATA
DAC-8562
13
10μF
0.1μF
0V
≤
V
OUT
≤
4.095V
+5V
CE
CLR
20
820
500pF
Figure 30. Unipolar Output Operation
Table III. Unipolar Code Table
Hexadecimal Number
in DAC Register
Decimal Number
in DAC Register
Analog Output
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+4.095
+2.049
+2.048
+2.047
0
Operating the DAC8562 on +12 V or +15 V Supplies Only
Although the DAC8562 has been specified to operate on a
single, +5 V supply, a single +5 V supply may not be available in
many applications. Since the DAC8562 consumes no more than
6 mA, maximum, then an integrated voltage reference, such as
the REF02, can be used as the DAC8562 +5 V supply. The
configuration of the circuit is shown in Figure 31. Notice that
the reference’s output voltage requires no trimming because of
the REF02’s excellent load regulation and tight initial output
voltage tolerance. Although the maximum supply current of the
DAC8562 is 6 mA, local bypassing of the REF02’s output with
at least 0. 1
μ
F at the DAC’s voltage supply pin is recommended
to prevent the DAC’s internal digital circuits from affecting the
DAC’s internal voltage reference.
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