- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376564 > DAC8562FP (ANALOG DEVICES INC) +5 Volt, Parallel Input Complete 12-Bit DAC PDF資料下載
參數(shù)資料
| 型號： | DAC8562FP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +5 Volt, Parallel Input Complete 12-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 636K |
| 代理商： | DAC8562FP |
DAC8562
REV. A
–14–
Decoding Multiple DAC8562s
The
CE
function of the DAC8562 can be used in applications
to decode a number of DACs. In this application, all DACs re-
ceive the same input data; however, only one of the DACs’
CE
input is asserted to transfer its parallel input register contents
into the DAC. In this circuit, shown in Figure 40, the
CE
tim-
ing is generated by a 74HC139 decoder and should follow the
DAC8562’s standard timing requirements. To prevent timing
errors, the 74HC139 should not be activated by its
ENABLE
input while the coded address inputs are changing. A simple
timing circuit, R1 and C1, connected to the DACs’
CLR
pins
resets all DAC outputs to zero during power-up.
MICROPROCESSOR INTERFACING
DAC-8562–MC68HC11 INTERFACE
The circuit illustrated in Figure 41 shows a parallel interface be-
tween the DAC8562 and a popular 8-bit microcontroller, the
M68HC11, which is configured in a single-chip operating
mode. The interface circuit consists of a pair of 74ACT11373
transparent latches and an inverter. The data is loaded into the
latches in two 8-bit bytes; the first byte contains the four most
significant bits, and the lower 8 bits are in the second byte. Data
is taken from the microcontroller’s port B output lines, and
three interface control lines,
CLR
,
CE
, and MSB/
LSB
, are con-
trolled by the M68HC11's PC2, PC1, and PC0 output lines, re-
spectively. To transfer data into the DAC, PC0 is set, enabling
U1’s outputs. The first data byte is loaded into U1 where the
four least significant bits of the byte are connected to
MSB–DB8. PC0 is then cleared; this latches U1’s inputs and
enables U2’s outputs. U2s outputs now become DB7–DB0.
The DAC output is updated with the contents of U1 and U2
when PC1 is cleared. The DAC’s
CLR
input, controlled by the
M68HC11’s PC2 output line, provides an asynchronous clear
function that sets the DAC’s output to zero. Included in this sec-
tion is the source code for operating the DAC-8562–M68HC11
interface.
V
CC
1G
1A
1B
2G
2A
2B
GND
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
12
1k
+5V
16
1
2
3
15
14
13
8
11
10
9
7
6
5
4
NC
NC
NC
NC
0.1μF
+5V
ENABLE
CODED
ADDRESS
+5V
C1
0.1μF
R1
1k
15
DAC-8562
#4
13
16
15
16
DAC-8562
#1
13
15
DAC-8562
#2
13
15
DAC-8562
#3
13
16
16
V
OUT1
V
OUT3
V
OUT4
V
OUT2
DATA
74HC139
Figure 40. Decoding Multiple DAC8562s Using the
CE
Pin
13
23
22
21
20
1
16
15
14
24
1
2
3
4
9
10
11
12
U1
C
1D
2D
3D
4D
5D
6D
7D
8D
OC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
13
23
22
21
20
1
16
15
14
24
1
2
3
4
9
10
11
12
U2
C
1D
2D
3D
4D
5D
6D
7D
8D
OC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLR
CE
MSB/ LSB
15
16
9
8
7
6
5
4
3
2
U3
CLR
CE
MSB
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
1
19
18
17
DB2
DB1
LSB
NC
NC
NC
NC
PC2
PC1
74ACT11373
*DAC-8562
74ACT11373
V
OUT
74HC04
1
*M6BHC11
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
*ADDITIONAL PINS OMITTED FOR CLARITY
2
13
Figure 41. DAC8562 to MC68HC11 Interface
相關PDF資料 |
PDF描述 |
|---|---|
| DAC8562FS | CONN TERM BLOCK 2POS 3.5MM PCB |
| DAC8562GBC | +5 Volt, Parallel Input Complete 12-Bit DAC |
| DAC8562EP | +5 Volt, Parallel Input Complete 12-Bit DAC |
| DAC8574EVM | DAC8574 Evaluation Module(DAC8574評估板) |
| DAC87 | 12-Bit Digital-to-Analog Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DAC8562FPZ | 功能描述:IC DAC 12BIT PARALLEL 5V 20-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| DAC8562FR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
| DAC8562FRU | 功能描述:IC DAC 12BIT PARALLEL 5V 20TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| DAC8562FRU-REEL7 | 功能描述:IC DAC 12BIT PARALLEL 5V 20TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| DAC8562FRUZ | 功能描述:IC DAC 12BIT PARALLEL 5V 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
發(fā)布緊急采購，3分鐘左右您將得到回復。