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參數(shù)資料
| 型號(hào)： | DAC8562FSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT PARALLEL 5V 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
DAC8562–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Resolution
N
Note 2
12
Bits
Relative Accuracy
INL
E Grade
–1/2
±1/4
+1/2
LSB
F Grade
–1
±3/4
+1
LSB
Differential Nonlinearity
DNL
No Missing Codes
–1
±3/4
+1
LSB
Zero-Scale Error
VZSE
Data = 000H
+1/2
+3
LSB
Full-Scale Voltage
VFS
Data - FFFH
3
E Grade
4.087
4.095
4.103
V
F Grade
4.079
4.095
4.111
V
Full-Scale Tempco
TCVFS
Notes 3, 4
±16
ppm/
°C
ANALOG OUTPUT
Output Current
IOUT
Data = 800H
±5
±7mA
Load Regulation at Half Scale
LDREG
RL = 402
to ∞, Data = 800
H
1
3
LSB
Capacitive Load
CL
No Oscillation4
500
pF
REFERENCE OUTPUT
Output Voltage
VREF
2.484
2.500
2.516
V
Output Source Current
IREF
Note 5
5
7
mA
Line Rejection
LNREJ
0.08
%/V
Load Regulation
LDREG
IREF = 0 to 5 mA
0.1
%/mA
LOGIC INPUTS
Logic Input Low Voltage
VIL
0.8
V
Logic Input High Voltage
VIH
2.4
V
Input Leakage Current
IIL
10
A
Input Capacitance
CIL
Note 4
10
pF
INTERFACE TIMING SPECIFICATIONS1, 4
Chip Enable Pulse Width
tCEW
30
ns
Data Setup
tDS
30
ns
Data Hold
tDH
10
ns
Clear Pulse Width
tCLRW
20
ns
AC CHARACTERISTICS4
Voltage Output Settling Time
6
tS
To
±1 LSB of Final Value
16
s
Digital Feedthrough
35
nV sec
SUPPLY CHARACTERISTICS
Positive Supply Current
IDD
VIH = 2.4 V, VIL = 0.8 V
3
6
mA
VIL = 0 V, VDD = +5 V
0.6
1
mA
Power Dissipation
PDISS
VIH = 2.4 V, VIL = 0.8 V
15
30
mW
VIL = 0 V, VDD = +5V
3
5
mW
Power Supply Sensitivity
PSS
V
DD = ± 5%
0.002
0.004
%/%
NOTES
1All input control signals are specified with t
r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
21 LSB = 1 mV for 0 to +4.095 V output range.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
–2–
(@ VDD = +5.0
5%, RS = No Load, –40 C
≤ T
A
≤ +85 C, unless otherwise noted)
REV. A
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