參數(shù)資料
型號(hào)： DC1010A-A
廠商： Linear Technology
文件頁(yè)數(shù)： 7/32頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2493
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1010A Design File
DC1010A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15
數(shù)據(jù)接口： I²C，串行
已用 IC / 零件： LTC2493
已供物品： 板
相關(guān)產(chǎn)品： LTC2493IDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493CDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493CDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493IDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493
15
2493fd
to permit that transfer. Devices addressed by the master
are considered a slave.
The LTC2493 can only be addressed as a slave. Once
addressed, it can receive configuration bits (channel
selection, rejection mode, speed mode) or transmit the
last conversion result. The serial clock line, SCL, is always
an input to the LTC2493 and the serial data line SDA is
bidirectional. The device supports the standard mode and
the fast mode for data transfer speeds up to 400kbits/s.
Figure 2 shows the definition of the I2C timing.
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from high to low while SCL is high. The bus is considered
to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from low to high while SCL is high. The
bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr)isgeneratedinsteadofaSTOPcondition.Therepeated
START timing is functionally identical to the START and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
low or issue a Not Acknowledge (NACK) by leaving the
SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the clock line (SCL) is low.
DATA FORMAT
After a START condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for
a read request and 0 for a write request. If the 7-bit ad-
dress matches the hard wired LTC2493’s address (one of
9 pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NACK by
leaving the SDA line high. If the conversion is complete,
the LTC2493 issues an ACK by pulling the SDA line low.
The LTC2493 has two registers. The output register (32
bits long) contains the last conversion result. The input
register (16 bits long) sets the input channel, selects the
temperature sensor, rejection mode, and speed mode.
SDA
SCL
S
Sr
P
S
tHD(SDA)
tHD(DAT)
tSU(STA)
tSU(STO)
tSU(DAT)
tLOW
tHD(SDA)
tSP
tBUF
tr
tf
tr
tf
tHIGH
2493 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
applicaTions inForMaTion
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