參數(shù)資料
型號(hào)： DC1010A-A
廠商： Linear Technology
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2493
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1010A Design File
DC1010A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 15
數(shù)據(jù)接口： I²C，串行
已用 IC / 零件： LTC2493
已供物品： 板
相關(guān)產(chǎn)品： LTC2493IDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493CDE#TRPBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493CDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493IDE#PBF-ND - IC ADC 24BIT DELTA SIG 14-DFN
LTC2493
17
2493fd
INPUT DATA FORMAT
The serial input word to the LTC2493 is 13 bits long and
is written into the device input register in two 8-bit words.
The first word (SGL, ODD, A2, A1, A0) is used to select
the input channel. The second word of data (IM, FA, FB,
SPD)isusedtoselectthefrequencyrejection,speedmode
(1×, 2×), and temperature measurement.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =
CH1),thefrequencyrejectiontosimultaneous50Hz/60Hz,
and 1× output rate (auto-calibration enabled). The first
conversion automatically begins at power-up using this
default configuration. Once the conversion is complete,
up to two words may be written into the device.
The first three bits of the first input word consist of two
preamble bits and one enable bit. Valid settings for these
three bits are 000, 100, and 101. Other combinations
should be avoided.
If the first three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
Figure 3a. Timing Diagram for Reading from the LTC2493
applicaTions inForMaTion
SLEEP
DATA OUTPUT
ACK BY
LTC2493
ACK BY
MASTER
SUB LSBs
START BY
MASTER
NACK BY
MASTER
LSB
R
MSB
SIG
D31
7
…
8
9
1
2
9
1
2
3
4
5
6
7
8
9
1
7-BIT
ADDRESS
2493 F03a
SCL
SDA
SLEEP
DATA INPUT
ACK BY
LTC2493
ACK BY
LTC2493
ACK BY
LTC2493
(OPTIONAL 2ND BYTE)
START BY
MASTER
SGL ODD
W
0
1
SCL
SDA
EN
A2
A1
A0
7
…
8
9
1
2
9
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
1
7-BIT ADDRESS
2493 F03b
IM
FA
EN2
FB
SPD
Figure 3b. Timing Diagram for Writing to the LTC2493
Table 3. Channel Selection
MUX ADDRESS
CHANNEL SELECTION
SGL
ODD/
SIGN
A2
A1
A0
0
1
2
3
COM
*0
0
IN+
IN–
0
1
IN+
IN–
0
1
0
IN–
IN+
0
1
0
1
IN–
IN+
1
0
IN+
IN–
1
0
1
IN+
IN–
1
0
IN+
IN–
1
0
1
IN+
IN–
*Default at power-up
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