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參數(shù)資料
| 型號(hào)： | DC1255A-A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1605 |
| 軟件下載： | QuikEval II System |
| 設(shè)計(jì)資源： | DC1255A Design Files DC1255A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±10 V |
| 已用 IC / 零件： | LTC1605 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC1605-2IG#PBF-ND - IC A/D CONV 16BIT SAMPLNG 28SSOP LTC1605-1IG#PBF-ND - IC A/D CONV 16BIT SAMPLNG 28SSOP LTC1605-2CN#PBF-ND - IC A/D CONV 16BIT SAMPLNG 28-DIP LTC1605-1CN#PBF-ND - IC A/D CONV 16BIT SAMPLNG 28-DIP LTC1605-1IN#PBF-ND - IC A/D CONV 16BIT SAMPLNG 28-DIP LTC1605-2IN#PBF-ND - IC A/D CONV 16BIT SAMPLNG 28-DIP LTC1605CG#PBF-ND - IC A/D CONV 16BIT SAMPLNG 28SSOP LTC1605AISW#TRPBF-ND - IC A/D CONV 16BIT SAMPLNG 28SOIC LTC1605ISW#TRPBF-ND - IC A/D CONV 16BIT SAMPLNG 28SOIC LTC1605-2CG#TRPBF-ND - IC A/D CONV 16BIT SAMPLNG 28SSOP 更多... |
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12
LTC1605
1605fc
APPLICATIONS INFORMATION
WU
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a read. Again it is recommended that both R/C and CS
return high within 3
s after the start of the conversion.
Output Data
The output data can be read as a 16-bit word or it can be
read as two 8-bit bytes. The format of the output data is
two’s complement. The digital input pin BYTE is used to
control the two byte read. With the BYTE pin low the first
eight MSBs are output on the D15 to D8 pins and the eight
LSBs are output on the D7 to D0 pins. When the BYTE pin
is taken high the eight LSBs replace the eight MSBs (Figure
10).
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figure 11 shows a
typical LTC1605 FFT plot which yields a SINAD of 87.5dB
and THD of – 102dB.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 11 shows a typical SINAD of 87.5dB
with a 100kHz sampling rate and a 1kHz input.
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20log
√V
2
2 + V32 + V42 ... + VN2
V1
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1605, a printed circuit board is
required. Layout for the printed circuit board should
ensure the digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
Figures 12 through 15 show a layout for a suggested
evaluation circuit which will help obtain the best perfor-
mance from the 16-bit ADC. Pay particular attention to the
design of the analog and digital ground planes. The DGND
pin of the LTC1605 can be tied to the analog ground plane.
Placing the bypass capacitor as close as possible to the
power supply, the reference and reference buffer output is
very important. Low impedance common returns for
these bypass capacitors are essential to low noise opera-
tion of the ADC, and the foil width for these tracks should
be as wide as possible. Also, since any potential difference
in grounds between the signal source and ADC appears as
an error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedance
as much as possible. The digital output latches and the
onboard sampling clock have been placed on the digital
ground plane. The two ground planes are tied together at
the power supply ground connection.
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