參數(shù)資料
型號: EVAL-AD7606-6EDZ
廠商: Analog Devices Inc
文件頁數(shù): 1/36頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR AD7606
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 200k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
在以下條件下的電源(標(biāo)準(zhǔn)): 90mW @ 200kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7606-6
已供物品:
8-/6-/4-Channel DAS with 16-Bit, Bipolar
Input, Simultaneous Sampling ADC
Data Sheet
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2010–2012 Analog Devices, Inc. All rights reserved.
FEATURES
8/6/4 simultaneously sampled inputs
True bipolar analog input ranges: ±10 V, ±5 V
Single 5 V analog supply and 2.3 V to 5 V VDRIVE
Fully integrated data acquisition solution
Analog input clamp protection
Input buffer with 1 M analog input impedance
Second-order antialiasing analog filter
On-chip accurate reference and reference buffer
16-bit ADC with 200 kSPS on all channels
Oversampling capability with digital filter
Flexible parallel/serial interface
SPI/QSPI/MICROWIRE/DSP compatible
Performance
7 kV ESD rating on analog input channels
95.5 dB SNR, 107 dB THD
±0.5 LSB INL, ±0.5 LSB DNL
Low power: 100 mW
Standby mode: 25 mW
64-lead LQFP package
APPLICATIONS
Power-line monitoring and protection systems
Multiphase motor control
Instrumentation and control systems
Multiaxis positioning systems
Data acquisition systems (DAS)
Table 1. High Resolution, Bipolar Input, Simultaneous
Sampling DAS Solutions
Resolution
Single-
Ended
Inputs
True
Differential
Inputs
Number of
Simultaneous
Sampling Channels
18 Bits
8
16 Bits
8
6
4
14 Bits
8
FUNCTIONAL BLOCK DIAGRAM
V1
V1GND
RFB
1M
RFB
CLAMP
SECOND-
ORDER LPF
T/H
V2
V2GND
RFB
1M
RFB
CLAMP
SECOND-
ORDER LPF
T/H
V3
V3GND
RFB
1M
RFB
CLAMP
SECOND-
ORDER LPF
T/H
V4
V4GND
RFB
1M
RFB
CLAMP
SECOND-
ORDER LPF
T/H
V5
V5GND
RFB
1M
RFB
CLAMP
SECOND-
ORDER LPF
T/H
V6
V6GND
RFB
1M
RFB
CLAMP
SECOND-
ORDER LPF
T/H
V7
V7GND
RFB
1M
RFB
CLAMP
SECOND-
ORDER LPF
T/H
V8
V8GND
RFB
1M
RFB
CLAMP
SECOND-
ORDER LPF
T/H
8:1
MUX
AGND
BUSY
FRSTDATA
CONVST A CONVST B RESET RANGE
CONTROL
INPUTS
CLK OSC
REFIN/REFOUT
REF SELECT
AGND
OS 2
OS 1
OS 0
DOUTA
DOUTB
RD/SCLK
CS
PAR/SER/BYTE SEL
VDRIVE
16-BIT
SAR
DIGITAL
FILTER
PARALLEL/
SERIAL
INTERFACE
2.5V
REF
REFCAPB REFCAPA
SERIAL
PARALLEL
REGCAP
2.5V
LDO
REGCAP
2.5V
LDO
AVCC
DB[15:0]
AD7606
08479-
001
Figure 1.
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