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參數(shù)資料
| 型號： | DC1561B |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 26/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR LTC4278 |
| 標準包裝： | 1 |
| 主要目的： | 電源管理，以太網供電（POE） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC4278 |
| 已供物品： | 板 |
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LTC4278
32
4278fc
APPLICATIONS INFORMATION
If we wanted a VIN-referred trip point of 36V, with 1.8V
(5%) of hysteresis (on at 36V, off at 34.2V):
RA = 1.8V
3.4
A
= 529k, use 523k
RB =
523k
36V
1.23V
– 1
= 18.5k, use 18.7k
Even with good board layout, board noise may cause
problems with UVLO. You can filter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 13c shows an alternate method of filtering by split-
ting the RA resistor with the capacitor. The split should put
more of the resistance on the UVLO side.
Converter Start-Up
The standard topology for the LTC4278 uses a third trans-
former winding on the primary side that provides both the
feedback information and local VCC power for the LTC4278
(Figure 14). This power bootstrapping improves converter
efficiency but is not inherently self-starting. Start-Up is
affected with an external
preregulator circuit that condi-
tions the input line voltage for the LTC4278 during start-up.
Upon application of power, CVCC is charged via the pre-
regulator, thereby providing an appropriate supply voltage
at the VCC pin for the LTC4278. This supply voltage is
typically in the range 7V and is used during start-up. After
converter startup, the third transformer winding becomes
energizedandisdesignedtogenerateahighervoltagethan
the preregulator. The higher voltage of the third winding
turns off QPR and provides an efficient method to power
the LTC4278.
Design of the VCC power circuitry involves selecting ap-
propriate voltage ranges for both the preregulator and
the third transformer winding. The preregulator voltage
is set as low as possible while ensuring it’s worst-case
minimum voltage is high enough to drive the switching
FETs gates during the startup period. The third winding
output voltage is selected to ensure that it’s worst-case
minimumvoltageexceedsthepreregulatorvoltageinorder
to turn off QPR. If the two voltage ranges overlap, the only
disadvantage is that a small degradation in efficiency may
occur. It is also necessary to verify that the worst-case
maximum winding voltage is not high enough to damage
the B-E junction of QPR.
Control Loop Compensation
Loop frequency compensation is performed by connect-
ing a capacitor network from the output of the feedback
amplifier (VCMP pin) to ground as shown in Figure 15.
Becauseofthesamplingbehaviorofthefeedbackamplifier,
compensation is different from traditional current mode
controllers. Normally only CVCMP is required. RVCMP can
be used to add a zero, but the phase margin improvement
traditionally offered by this extra resistor is usually already
accomplishedbythenonzerosecondarycircuitimpedance.
CVCMP2 can be used to add an additional high frequency
pole and is usually sized at 0.1 times CVCMP.
17
RVCMP
VCMP
CVCMP
4278 F15
CVCMP2
Figure 15. VCMP Compensation Network
Figure 14. Typical Power Bootstrapping
4278 F14
VIN
VCC
CVCC
QPR
LTC4278
PG
FB
GND
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