參數(shù)資料
型號(hào): DC1562A-K
廠商: Linear Technology
文件頁(yè)數(shù): 5/26頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL LTC6994-1
設(shè)計(jì)資源: DC1562A Design Files
DC1562A Schematic
特色產(chǎn)品: TimerBlox?
標(biāo)準(zhǔn)包裝: 1
系列: TimerBlox®
主要目的: 定時(shí),延遲線路
嵌入式:
已用 IC / 零件: LTC6994-1
主要屬性: 100ms 下降沿延遲
次要屬性: 2.25 V ~ 5.5 V 電源
已供物品:
LTC6994-1/LTC6994-2
13
699412fb
operaTion
Figure 3. Rising-Edge Delayed Timing Diagram (LTC6994-1, POL = 0)
Figure 4. Falling-Edge Delayed Timing Diagram (LTC6994-1, POL = 1)
Edge-Controlled Delay
The LTC6994 is a programmable delay or pulse qualifier.
It can perform noise filtering, which distinguishes it from
a delay line (which simply delays all input transitions).
WhenthevoltageontheLTC6994inputpin(IN)transitions
low or high, the LTC6994 can delay the corresponding
output transition by any time from 1s to 33.6 seconds.
LTC6994-1 Functionality
Figures3detailsthebasicoperationoftheLTC6994-1when
configured to delay rising edge transitions (POL = 0). A
rising edge on the IN pin initiates the timing. OUT remains
low for the duration of tDELAY. If IN stays high then OUT
will transition high after this time. If the input doesn’t
remain high long enough for OUT to transition high then
the timing will restart on each successive rising edge. In
this way, the LTC6994-1 can serve as a pulse qualifier,
filtering out noisy or short signals.
On a falling edge at the input, the output will follow im-
mediately (after a short propagation delay tPD).Note that
the output pulse width may be extremely short if IN falls
immediately after OUT rises.
Figure 4 details the operation of the LTC6994-1 when
configured to delay falling edges (POL = 1).
IN
OUT
tDELAY
tPD
tDELAY
tPD
699412 F03
tWIDTH
tPD
IN
OUT
tDELAY
tPD
tDELAY
tPD
tWIDTH
tDELAY
699412 F04
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