參數(shù)資料
型號: DC1562A-K
廠商: Linear Technology
文件頁數(shù): 6/26頁
文件大小: 0K
描述: BOARD EVAL LTC6994-1
設(shè)計(jì)資源: DC1562A Design Files
DC1562A Schematic
特色產(chǎn)品: TimerBlox?
標(biāo)準(zhǔn)包裝: 1
系列: TimerBlox®
主要目的: 定時(shí),延遲線路
嵌入式:
已用 IC / 零件: LTC6994-1
主要屬性: 100ms 下降沿延遲
次要屬性: 2.25 V ~ 5.5 V 電源
已供物品:
LTC6994-1/LTC6994-2
14
699412fb
operaTion
LTC6994-2 Functionality
Figures 5 details the basic operation of the LTC6994-2
when configured for noninverting operation (POL = 0). As
before, a rising edge on the IN pin initiates the timing and,
if IN remains high, OUT will transition high after tDELAY.
UnliketheLTC6994-1,fallingedgesaredelayedinthesame
way. When IN transitions low, OUT will follow after tDELAY.
If the input doesn’t remain high or low long enough for
OUT to follow, the timing will restart on the next transition.
Also unlike the LTC6994-1, the output pulse width can
never be less than tDELAY. Therefore, the LTC6994-2 can
generate pulses with a defined minimum width.
Figure 6 details the operation of the LTC6994-2 when the
output is inverted (POL = 1).
Figure 5. Both Edges Delayed Timing Diagram (LTC6994-2, POL = 0)
Figure 6. Both Edges Delayed (Inverting) Timing Diagram (LTC6994-2, POL = 1)
IN
OUT
tDELAY
tPD
tWIDTH
tPD
tDELAY
tPD
tDELAY
699412 F05
IN
OUT
tDELAY
tPD
tWIDTH
tDELAY
699412 F06
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