參數(shù)資料
型號： DC745A
廠商： Linear Technology
文件頁數(shù)： 6/28頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2433-1
軟件下載： QuikEval System
設(shè)計(jì)資源： DC745A Design File
DC745A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2433-1
已供物品： 板
相關(guān)產(chǎn)品： LTC2433-1IMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1CMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1IMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1CMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1IMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP
LTC2433-1CMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP
LTC2433-1IMS-ND - IC CONV A/D 16BIT DIFF 10-MSOP
LTC2433-1CMS-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1
14
24331fa
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. Data is shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 19th rising edge of SCK. On the 19th
falling edge of SCK, the device begins a new conversion.
SDO goes HIGH (EOC = 1) indicating a conversion is in
progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
19th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for abort-
ing an invalid conversion cycle or synchronizing the start
of a conversion.
Figure 7. External Serial Clock, Reduced Data Output Length
SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSION
SLEEP
TEST EOC (OPTIONAL)
TEST EOC
DATA OUTPUT
Hi-Z
CONVERSION
24331 F07
MSB
SIG
“O”
BIT 4
BIT 14
BIT 5
BIT 15
BIT 16
BIT 17
EOC
BIT 18
BIT 0
EOC
Hi-Z
TEST EOC
SLEEP
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
110
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2433-1
3-WIRE
SPI INTERFACE
APPLICATIO S I FOR ATIO
WU
UU
相關(guān)PDF資料
PDF描述
RMM08DRXS CONN EDGECARD 16POS DIP .156 SLD
SC75B-100 INDUCTOR SMD 10UH 2.30A 2.52MHZ
RBM11DRAH CONN EDGECARD 22POS R/A .156 SLD
CI160808-12NJ INDUCTOR 12NH 300MA SMD
0210490986 CABLE JUMPER 1.25MM .030M 29POS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DC746A 功能描述:BOARD DELTA SIGMA ADC LTC2412 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:QuikEval™ 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
DC74HC259 制造商:TI 制造商全稱:Texas Instruments 功能描述:High Speed CMOS Logic 8-Bit Addressable Latch
DC-750 制造商:Bivar 功能描述:CARD GUIDE DEEP 7.5" 0.08" BK
DC-750-102 制造商:Bivar 功能描述:CARD GUIDE DEEP 7.5" 0.102" BK
DC-750-102-CI 制造商:Bivar 功能描述:CARD GUIDE INSERT 7.5" 0.102" BK
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*