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參數(shù)資料
| 型號(hào)： | DC806A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC1867 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC806A Design File DC806A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC1867 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC1867ACGN#PBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867LIGN#PBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP LTC1867IGN#PBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867LACGN#PBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP LTC1867CGN#PBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867IGN#TRPBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867AIGN#PBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867LAIGN#PBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP LTC1867LCGN#PBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP LTC1867LACGN#TRPBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP 更多... |
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LTC1863/LTC1867
8
18637fa
TIMING DIAGRAMS
t5 (SDI Setup Time Before SCK↑),
t6 (SDI Hold Time After SCK↑)
50%
t3
0.4V
t7 (SLEEP Mode Wake-Up Time)
t7
SCK
CS/CONV
t8 (BUS Relinquish Time)
t8
CS/CONV
SDO
2.4V
t4 (SDO Valid After CONV↓)
t4
CS/CONV
SDO
2.4V
0.4V
t6
2.4V
0.4V
t5
SCK
SDI
2.4V
0.4V
2.4V
0.4V
SDO
1867 TD
SLEEP BIT (SLP = 0)
READ-IN
10%
90%
Hi-Z
t1 (For Short Pulse Mode)
t2 (SDO Valid Before SCK↑),
t3 (SDO Valid Hold Time After SCK↓)
t1
CS/CONV
t2
SCK
50%
Overview
The LTC1863/LTC1867 are complete, low power multi-
plexed ADCs. They consist of a 12-/16-bit, 200ksps capaci-
tive successive approximation A/D converter, a precision
internal reference, a congurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 1.5μs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most signicant bit (MSB) to the least signicant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low-power, differential
comparator. At the end of a conversion, the DAC output
balances the analog input. The SAR contents (a 12-/16-bit
data word) that represent the analog input are loaded into
the 12-/16-bit output latches.
APPLICATIONS INFORMATION
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| DC-8076-WH | 功能描述:機(jī)架和機(jī)柜 RO 563-DC-8076-BT RoHS:否 制造商:Hammond Manufacturing 產(chǎn)品:Racks 類型:Table Top 外部寬度: 外部高度: 外部深度: 面板高度: 面板寬度: |
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