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參數(shù)資料
| 型號(hào)： | DC846A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2447 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC846A Design File DC846A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 8k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2447 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2447IUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2447CUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2447IUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2447CUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN |
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LTC2446/LTC2447
14
24467fa
Speed Multiplier Mode
In addition to selecting the speed/resolution, a speed
multiplier mode is used to double the output rate while
maintaining the selected resolution. The last bit of the 5-bit
speed/resolution control word (TWOX, see Table 4) deter-
mines if the output rate is 1x (no speed increase) or 2x
(double the selected speed).
While operating in the 1x mode, the device combines two
internal conversions for each conversion result in order to
remove the ADC offset. Every conversion cycle, the offset
and offset drift are transparently calibrated greatly simpli-
fying the user interface. The conversion result has no
latency. The first conversion following a newly selected
speed/resolution and/or input/reference is valid. This is
identical to the operation of the LTC2440, LTC2444,
LTC2445, LTC2448, LTC2449, LTC2414 and LTC2418.
While operating in the 2x mode, the device performs a
running average of the last two conversion results. This
automatically removes the offset and drift of the device
while increasing the output rate by 2x. The resolution
(noise) remains the same as the 1x mode. If a new
channel/reference is selected, the conversion result is
valid for all conversions after the first conversion (one
cycle latency). If a new speed/resolution is selected, the
first conversion result is valid but the resolution (noise) is
a function of the running average. All subsequent conver-
sion results are valid. If the mode is changed from either
1x to 2x or 2x to 1x without changing the resolution or
channel, the first conversion result is valid.
If an external buffer/amplifier circuit is used for the
LTC2447, the 2x mode can be used to increase the settling
time of the amplifier between readings. While operating in
the 2x mode, the multiplexer output (input to the external
buffer/amplifier) is switched at the end of each conversion
cycle. Prior to concluding the data out/in cycle, the analog
multiplexer output is switched. This occurs at the end of
the conversion cycle (just prior to the data output cycle)
for auto calibration. The time required to read the conver-
sion enables more settling time for the external buffer/
amplifier. The offset/offset drift of the external amplifiers
are automatically removed by the converter’s auto calibra-
tion sequence for both the 1x and 2x speed modes.
While operating in the 1x mode, if a new input channel/
reference is selected the multiplexer is switched on the
falling edge of the 14th SCK (once the complete data input
word is programmed). The remaining data output se-
quence time can be used to allow the external buffer/
amplifier to settle.
BUSY
The BUSY output (Pin 2) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion is
complete, BUSY goes LOW indicating the conversion is
complete and data out is ready. The part now enters the
LOW power sleep state. BUSY remains LOW while data is
shifted out of the device and SDI is shifted into the device.
It goes HIGH at the conclusion of the data input/output
cycle indicating a new conversion has begun. This rising
edge may be used to flag the completion of the data read
cycle.
SERIAL INTERFACE TIMING MODES
The LTC2446/LTC2447’s 3- or 4-wire interface is SPI and
MICROWIRE compatible. This interface offers several flex-
ible modes of operation. These include internal/external
serial clock, 3- or 4-wire I/O, single cycle conversion and
autostart. The following sections describe each of these
serial interface timing modes in detail. In all these cases,
the converter can use the internal oscillator (FO = LOW) or
an external oscillator connected to the FO pin. Refer to
Table 5 for a summary.
Table 5. LTC2446/LTC2447 Interface Timing Modes
CONVERSION
DATA
CONNECTION
SCK
CYCLE
OUTPUT
AND
CONFIGURATION
SOURCE
CONTROL
WAVEFORMS
External SCK, Single Cycle Conversion
External
CS and SCK
Figures 4, 5
External SCK, 3-Wire I/O
External
SCK
Figure 6
Internal SCK, Single Cycle Conversion
Internal
CS
↓
CS
↓
Figures 7, 8
Internal SCK, 3-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 9
APPLICATIO S I FOR ATIO
WU
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