is zero, the common mode input current (IIN++ II" />
參數(shù)資料
型號: DC955A
廠商: Linear Technology
文件頁數(shù): 11/34頁
文件大?。?/td> 0K
描述: BOARD DELTA SIGMA ADC LTC2483
軟件下載: QuikEval System
設(shè)計資源: DC955A Design File
DC955A Schematic
標(biāo)準(zhǔn)包裝: 1
系列: Easy Drive™, QuikEval™
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 6.8
數(shù)據(jù)接口: I²C,串行
工作溫度: 0°C ~ 70°C
已用 IC / 零件: LTC2483
已供物品:
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LTC2483
2483fc
is zero, the common mode input current (IIN++ IIN–)/2 is
proportional to the difference between the common mode
input voltage (VINCM) and the common mode reference
voltage (VREFCM).
In applications where the input common mode voltage
is equal to the reference common mode voltage, as in
the case of a balance bridge type application, both the
differential and common mode input current are zero.
The accuracy of the converter is unaffected by settling
errors. Mismatches in source impedances between IN+
and INalso do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VINCM and VREFCM. For a reference
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74A. This common mode input current has no effect
on the accuracy if the external source impedances tied
to IN+ and INare matched. Mismatches in these source
impedances lead to a fixed offset error but do not affect
the linearity or full-scale reading. A 1% mismatch in 1k
source resistances leads to a 15ppm shift (74V) in offset
voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the com-
mon mode input current varies proportionally with input
voltage. For the case of balanced input impedances, the
common mode input current effects are rejected by the
large CMRR of the LTC2483 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1k source resistances lead to
worst-case gain errors on the order of 15ppm or 1 LSB
(for 1V differences in reference and input common mode
voltage). Table 5 summarizes the effects of mismatched
source impedance and differences in reference/input
common mode voltages.
applicaTions inFormaTion
Themagnitudeofthedynamicinputcurrentdependsupon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5%.Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN, the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1V typical and 10V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2483 samples the differential
reference pins REF+ and REFtransferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
Table 5. Suggested Input Configuration for LTC2483
BALANCED INPUT
RESISTANCES
UNBALANCED INPUT
RESISTANCES
Constant
VIN(CM) – VREF(CM)
CEXT > 1nF at Both
IN+ and IN. Can Take
Large Source Resistance
with Negligible Error
CEXT > 1nF at Both IN+
and IN. Can Take Large
Source Resistance.
Unbalanced Resistance
Results in an Offset
Which Can Be Calibrated
Varying
VIN(CM) – VREF(CM)
CEXT > 1nF at Both IN+
and IN. Can Take Large
Source Resistance with
Negligible Error
Minimize IN+ and IN
Capacitors and Avoid
Large Source Impedance
(<5k Recommended)
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