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參數(shù)資料
| 型號(hào)： | DDC101 |
| 英文描述： | 20-BIT ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 20位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 21/27頁 |
| 文件大?。?/td> | 346K |
| 代理商： | DDC101 |
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21
DDC101
Figure 21 shows the frequency response of the DDC101 and
an ideal integrator with the same integration time. In this
comparison, the DDC101 has greater bandwidth to the first
null, but it also has greater out of band attenuation which
reduces broadband noise significantly. If desired, the fre-
quency response of the ideal integrator can be produced by
passing the DDC101 output through an external digital
filtering function which has the frequency response from DC
to Nyquist of
This has the effect of further attenuating undesired signals
(noise) outside the “passband”, further increasing the signal-
to-noise ratio of the DDC101 and closely emulating the ideal
integrator’s signal accumulation characteristics.
SYSTEM SETUP
After power up, the Reset System and FDS signal inputs
should be held low (active), while the SETUP register is
loaded by the user. After the SETUP register is loaded, the
Reset System input should transition to inactive while the
FDS input remains active. The FDS should transition to
inactive at the start of operation. Thereafter, Reset System
should stay inactive and the FDS should be used to control
each integration cycle.
SETUP INPUT
Software Control
Many of the options of the DDC101 are set through a serial
bit stream transmitted by the user into the SETUP Input pin.
The 12-bit word transmitted into the SETUP Input is used to
set the following four options, in sequence:
1. Acquisition Time Control, K
2. Oversampling Control
Samples/Integration, M
3. Multiple Integration Control
Integrations/Conversion, L
4. Unipolar or Bipolar Input Range
5. Output Format
Total for SETUP
See Figure 5: SETUP Timing Diagram.
2 bits
4 bits
4 bits
1 bit
1 bit
12 bits
Acquisition Time Control, K
This signal sets the acquisition time (K clock periods) and
controls the use of Correlated Double Sampling. The acqui-
sition time occurs at the start of each new integration. The
acquisition time control can be set to four options: “no
CDS”, 1, 16 or 32 clock periods. For typical continuous
integration applications, K = 16 is recommended. The acqui-
sition time always begins with one clock period for reset.
This reset clock period is followed by 0, 15 or 31 clock
periods for signal acquisition. Correlated Double Sampling
is activated if the initial acquisition time is set to 1, 16 or 32
clock periods. Correlated Double Sampling is disabled and
the Initial Data Point is not acquired if “no CDS” is selected.
FIGURE 21. Comparison of DDC101 with Ideal Integrator.
When Correlated Double Sampling is activated, the DDC101
acquires the initial data point for error correction as part of
each conversion. At the end of the conversion cycle, the
initial data point is subtracted from the final data point. The
errors that are corrected with CDS are charge injection,
kT/C noise, and DDC101 voltage offset. When Correlated
Double Sampling is deactivated, the initial data point is not
taken.
0
–5
–10
–15
–20
–25
–30
–35
–40
100
1k
10k
100k
Frequency (Hz)
G
DDC101 with N = 2000;
L = 1; M = 256; K = 16;
T
CONV
= T
= 2MHz/N = 1ms
f
MEAS
= 2MHz/(N-M-K) = 1.16kHz
Comparison of DDC101 with Ideal Integrator
Ideal Integrator
with T
INT
= 1ms
f
MEAS
Nyquist
(f
CONV
/2)
f
CONV
sin(
π
fT
INT
)
π
fT
INT
π
fT
MEAS
sin(
π
fT
MEAS
)Msin(
π
f / f
CLK
)
fM / f
CLK
)
.
FIGURE 20. Product of Frequency Response of Basic Inte-
gration and Oversampling; 1ms Integration
Time, 32 Oversamples.
RESET
CLOCKS
ACQUISITION
CLOCKS
K
CDS
“No CDS”
1
16
32
1
1
1
1
0
0
Disabled
Enabled
Enabled
Enabled
15
31
TABLE IX. Acquisition Time Control, K.
0
–5
–10
–15
–20
–25
–30
–35
–40
100
1k
10k
100k
Frequency (Hz)
G
N = 2000
M = 32
K = 16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDC101P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DDC101U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Anlg-to-Dig Converter RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC101UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Anlg-to-Dig Converter RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC1021 | 制造商:MPSIND 制造商全稱:MPS Industries, Inc. 功能描述:3W, Wide Input Range SMD, Single & Dual Output DC/DC Converters |
| DDC1022 | 制造商:MPSIND 制造商全稱:MPS Industries, Inc. 功能描述:3W, Wide Input Range SMD, Single & Dual Output DC/DC Converters |
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