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參數(shù)資料
| 型號： | DDC101 |
| 英文描述： | 20-BIT ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 20位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大?。?/td> | 346K |
| 代理商： | DDC101 |
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DDC101
8
FIGURE 6. DATA TRANSMIT Timing Diagram.
FIGURE 4. Conversion Timing Diagrams.
Input
Range
Output
Format
SETUP In
DATA CLOCK
(4MHz, max for setup)
ACQ
LSB
t
5
RESET SETUP In
ACQ
MSB
Read
t
7
Read
Read
Read
t
6
FIGURE 5. Input/Output Timing Diagram—SETUP Timing Diagram.
SYSTEM
CLOCK
DATA VALID
Out
DATA TRANSMIT
In
DATA OUTPUT
DATA CLOCK
(8MHz, max for data)
t
10
DDC(1)
Bit 1, MSB
DDC(n)
Bit 21, LSB
DDC
(n+1)
Bit 1
Output Disabled
Last DDC
Bit 21
Output Enabled
Output Disabled
t
12
Data can be read on rising or falling edge of Data Clock
DATA TRANSMIT In resets DATA VALID Out.
t
9
t
11
t
13
t
17
t
8
Continuous Integration Timing
Non-Continuous Integration Timing
SYSTEM
CLOCK
FDS In
Internal
Oversampling
Interval
Internal
Reset
SYSTEM
CLOCK
FDS In
Internal
Oversampling
Interval
Internal
Reset
FDS In should be coincident with negative clock.
FDS initiates oversampling period.
M Clock Periods
End of oversample period
initiates reset for next integration.
FDS In should be coincident with negative clock.
FDS initiates oversampling period.
End of FDS In
initiates end of Internal Reset.
End of oversample
period initiates
reset.
When Internal Reset period ends,
next integration begins.
DATA VALID
Out
t
2
t
1
t
3
DATA VALID Out
Next integration begins when 1 clock
period wide Internal Reset ends.
M Clock Periods
t
4
T
INT
'
T
INT
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| DDC112 | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| DDC112U | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| DDC112UK | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| DDC118 | Octal Current Input 20-Bit Analog-To-Digital Converter |
| DDC118IRTCR | Octal Current Input 20-Bit Analog-To-Digital Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDC101P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DDC101U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Anlg-to-Dig Converter RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC101UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Anlg-to-Dig Converter RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC1021 | 制造商:MPSIND 制造商全稱:MPS Industries, Inc. 功能描述:3W, Wide Input Range SMD, Single & Dual Output DC/DC Converters |
| DDC1022 | 制造商:MPSIND 制造商全稱:MPS Industries, Inc. 功能描述:3W, Wide Input Range SMD, Single & Dual Output DC/DC Converters |
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