參數(shù)資料
型號: DG636EN-T1-E4
廠商: Vishay Siliconix
文件頁數(shù): 1/14頁
文件大?。?/td> 0K
描述: IC SWITCH DUAL SPDT 16-MINIQFN
標準包裝: 1
功能: 開關(guān)
電路: 2 x SPDT
導通狀態(tài)電阻: 170 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 2.7 V ~ 12 V,± 2.7 V ~ 5 V
電流 - 電源: -500nA,500nA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN
供應商設備封裝: 16-迷你型QFN(1.8x2.6)
包裝: 標準包裝
其它名稱: DG636EN-T1-E4DKR
Vishay Siliconix
DG636
Document Number: 69901
S10-1815-Rev. D, 02-Aug-10
www.vishay.com
1
0.5 pC Charge Injection, 100 pA Leakage,
Dual SPDT Analog Switch
DESCRIPTION
The DG636 is an analog CMOS, dual SPDT switch,
designed to operate from a + 2.7 V to + 12 V single supply or
from ± 2.7 V to ± 5.0 V, dual supplies. The DG636 is fully
specified at + 3 V, + 5 V and ± 5 V. All control logic inputs have
guaranteed 2 V logic high limits when operating from + 5 V or
± 5 V supplies and 1.4 V when operating from a 3 V supply.
The DG636 switches conduct equally well in both directions
and offer rail to rail analog signal handling. < 1 pC low charge
injection, coupled with very low switch capacitance and
leakage current makes this product ideal for use in precision
instrumentation applications. Operating temperature range
is specified from - 40 °C to + 125 °C. The DG636 is available
in 14 lead TSSOP and the space saving 1.8 mm x 2.6 mm
miniQFN package.
FEATURES
Ultra low charge injection (± 0.5 pC, typ. over
the full analog signal range)
Leakage current < 0.5 nA max. at 85 °C
(for DG636EQ-T1-E3)
Low switch capacitance (Csoff, 2 pF typ.)
Low RDS(on) - 115 max.
Fully specified with single supply operation at 3.0 V, 5.0
V and dual supplies at ± 5.0 V
Low voltage, 2.5 V CMOS/TTL compatible
600 MHz, - 3 dB bandwidth
Excellent isolation and crosstalk performance (typ. > - 60
dB at 10 MHz)
Fully specified from - 40 °C to 85 °C and - 40 °C to
+ 125 °C
14 pin TSSOP and 16 pin miniQFN package (1.8 mm x
2.6 mm)
Compliant to RoHS directive 2002/95/EC
APPLICATIONS
High-end data acquisition
Medical instruments
Precision instruments
High speed communications applications
Automated test equipment
Sample and hold applications
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
ENABLE = Hi, all switches are controlled by
addr pins. ENABLE = Lo, all switches are off.
V-
S1B
S1A
1
2
3
4
7
8
9
10
11
12
5
8
7
6
13
14
15
16
A1
NC
A0
NC
Top View
DG636
mQFN-16
ENABLE
D1
S2B
D2
NC
V+
GND
S2A
NC
Logic
DG636
TSSOP14
Top View
GND
S1B
A0
V+
ENABLE
V-
S2B
D2
9
11
12
S1A
NC
S2A
A1
8
14
13
NC
D1
3
4
5
6
1
2
7
Logic
Pin 1
Device Marking: Rxx for DG636
(miniQFN16)
xx = Date/Lot Traceability Code
Rxx
RoHS
COMPLIANT
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