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參數(shù)資料
| 型號(hào)： | DG884DN-E3 |
| 廠商： | Vishay Siliconix |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO MULTIPLEXER 8X4 |
| 標(biāo)準(zhǔn)包裝： | 300 |
| 功能： | 視頻交叉點(diǎn)開關(guān) |
| 電路： | 1 x 8:4 |
| 導(dǎo)通狀態(tài)電阻： | 90 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 10 V ~ 18 V，±10 V ~ 15 V |
| 電流 - 電源： | 1.5mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
Document Number: 70071
S-71241–Rev. H, 25-Jun-07
www.vishay.com
7
Vishay Siliconix
DG884
TIMING DIAGRAMS
Figure 1. Input Timing Requirements
tSW
tAW
Presetting Device A
CS for
Device A
CS for
Device B
Address
B0
B1
Address
A0
A3
WR
SALVO
RS
I/O
Select Output 1
Presetting Device B
Donít Care
Select Output 2
Output N
Select Input
Input
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
tWA
tAW
tWA
tWP
tSP
tRS
tCW
tCA
tIA
tWS
tAW
tWC
tSP
tSW
tCW
tWS
Input
Figure 2. Output Timing Requirements
PARAMETER DEFINITIONS
Symbol
Parameter
Description
TAW
Address to Write
Minimum time address must be valid before WR goes high
TWA
Write to Address
Minimum time address must remain valid after WR pulse goes high
TWP
WR Pulse
Minimum time of WR pulse width to write address into Next Event latches
TCW
Chip Select to WR
Minimum time chip select must be valid before a WR pulse
TWC
WR to Chip Select
Minimum time chip select must remain valid after WR pulse
TSP
SALVO Pulse
Minimum time of SALVO pulse width
TWS
WR to SALVO
Minimum time from WR pulse to SALVOto load new address
TSW
SALVO to WR
Minimum time from SALVO pulse to WR to load current address
TIA
I/O to Address In
Minimum time I/O must be valid before address applied
TRS
RS to SALVO
Minimum time RS must be valid before SALVO pulse
TIO
I/O to Output
Minimum time I/O must be valid before address output valid
TAO
Address to Output
Minimum time address BX must be valid until address AX output valid
TCO
CS to Output
Minimum time CS must be valid until AX output is valid
TCA
CS to Address In
Minimum time CS must be valid before address applied if I/O is high
tAO
t AO
CS for
Device A
CS for
Device B
Interrogating Device A
Address
B0
B1
Address
A0
A3
WR
SALVO
RS
I/O
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
tIO
Select Current
Event Latch 1
Select Current
Event Latch
Interrogating Device B
Output
tC
O
tAO
Latch N
tCA
Out N
tC
O
tC
A
tAO
tIA
Address Output 1
Address Output
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