參數(shù)資料
型號: DIR1701E2K
英文描述: DIGITAL AUDIO INTERFACE RECEIVER
中文描述: 數(shù)字音頻接口接收機
文件頁數(shù): 7/19頁
文件大?。?/td> 290K
代理商: DIR1701E2K
DIR1701
SLAS331
APRIL 2001
7
www.ti.com
system clock output (continued)
30
25
20
15
10
5
0
5
100
1 k
f
Frequency
Hz
10 k
100 k
M
Figure 2. Jitter Attenuator Characteristics With Specified Loop Filter
Table 2. Selectable Crystal Oscillators
SYSTEM CLOCK fS
128
CRYSTAL
BRSEL CONNECTED TO
12 MHz
CSBIT
256
12 MHz
OPEN or DGND
384
12 MHz
BFRAME
512
16 MHz
BFRAME
Table 3. System Clock Selection
SCF1
SCF0
SYSTEM CLOCK
LOW
LOW
128 fS
256 fS
384 fS
512 fS
LOW
HIGH
HIGH
LOW
HIGH
HIGH
Table 4. System Clock and Data Output Operation
CONDITIONS
CLOCK AND DATA OUTPUTS
S/PDIF DATA
SCKO
BCKO
LRCKO
DOUT
BRATE
UNLOCK
CS. UR BIT
AD. EMFLG
After RESET
Unknown
(128, 256, 384, 512 fS)
PLL
(128, 256, 384, 512 fS)
HOLD
(128, 256, 384, 512 fS)
Unknown
(64 fS)
PLL
(64 fS)
HOLD
(64 fS)
Unknown
(1 fS)
PLL
(1 fS)
HOLD
(1 fS)
MUTE
LOW
HIGH
LOW
LOW
YES
DATA
DETECT
LOW
DATA
DATA
NO
MUTE
HOLD
HIGH
HOLD
HOLD
Holds the latest tracked frequency.
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DISADVANTAGE Disadvantage of On-Chip Transient Protection (105k)
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