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參數(shù)資料
| 型號(hào)： | DIR1701E2K |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數(shù)字音頻接口接收機(jī) |
| 文件頁(yè)數(shù)： | 9/19頁(yè) |
| 文件大?。?/td> | 290K |
| 代理商： | DIR1701E2K |
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DIR1701
SLAS331
–
APRIL 2001
9
www.ti.com
relation between audio-data-output timing and PLL condition indicator timing
When the analog PLL is still unlocked and the S/PDIF signal starts, after at least ten rising edges, the S/PDIF
decoder can detect the incoming S/PDIF signal. The DOUT pin becomes LOW (MUTE) until the analog PLL
locks. This MUTE period t
INT
is less than 1 ms (the analog PLL lockup time is less than 0.5 ms). When the
decoder detects that incoming S/PDIF signal has stopped, UNLOCK goes HIGH at the next LRCKO transition.
SCKO keeps its frequency at the latest tracked bit rate.
When S/PDIF signal is not present after removal of reset, the frequency of the DIR1701 audio clocks (SCKO,
BCKO, LRCKO) is not known.
2
1
Mute
L
H
31
32
Mute
Unlock
Lock
PLL
Condition
UNLOCK
LRCKO
BCKO
DOUT
Figure 4. Relation Between Audio Data Output Timing and UNLOCK Flag Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DIR1701 | DIGITAL AUDIO INTERFACE RECEIVER |
| DIR1701E | DIGITAL AUDIO INTERFACE RECEIVER |
| DIR1703 | DIGITAL AUDIO INTERFACE RECEIVER |
| DIR1703E | DIGITAL AUDIO INTERFACE RECEIVER |
| DISADVANTAGE | Disadvantage of On-Chip Transient Protection (105k) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DIR1703 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:96-kHz, 24-Bit Digital Audio Interface Receiver |
| DIR1703E | 功能描述:IC DIGTAL AUD INTRFC RCVR 28SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,240 系列:GD 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):3/5 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:20-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:20-PDIP 包裝:管件 |
| DIR1703E/2K | 制造商:Texas Instruments 功能描述:Audio Interface Receiver 28-Pin SSOP T/R 制造商:Texas Instruments 功能描述:AUD INTRFC RCVR 28SSOP - Tape and Reel |
| DIR-600/E | 制造商:D-Link Networks 功能描述: |
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