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參數(shù)資料
| 型號： | DIR1703E |
| 英文描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 中文描述： | 數(shù)字音頻接口接收機(jī) |
| 文件頁數(shù)： | 10/19頁 |
| 文件大小： | 236K |
| 代理商： | DIR1703E |
SLES007
–
JULY 2001
10
www.ti.com
bit rate detection
By using the SpAct frequency estimator (not the S/PDIF channel status bit), the DIR1703 automatically detects
the sample rate of an incoming S/PDIF signal and indicates the frequency at the BRATE pins.
Table 6 lists the frequency ranges reported. Except for 88.2 and 96 kHz, these sample rates are the same as
the channel status bit defined in the S/PDIF specifications. When the bit-rate is 88.2 or 96 kHz the indicator
shows the same HL value. This state is not defined in the S/PDIF specifications.
Table 6. Incoming Sample Frequency Bits
SAMPLING RATE
32 kHz
44.1 kHz
48 kHz
88.2 kHz
96 kHz
BRATE1
HIGH
LOW
LOW
HIGH
HIGH
BRATE0
HIGH
LOW
HIGH
LOW
LOW
timing specification for PLL operation
lock-up time
Lock
L
H
tINT< 1 ms
Unlock
DIN Start
PLL
Condition
PLL Status
Indicator Pin
Site UNLOCK
Figure 3. PLL Lock Up Timing
relation between audio-data-output timing and PLL condition indicator timing
In the PLL clock operation mode, when the S/PDIF signal is not detected after reset removal, audio clocks
(SCKO, BCKO, LRCKO) which are not related to S/PDIF signal are generated by SpAct. The bit rate can be
selected by setting pin BRSEL. If BRSEL is OPEN or connected to DGND, the default bit rate frequency is set
to 48 kHz. If BRSEL is connected to one of the output pins BFRAME, EMFLG, URBIT, or CSBIT, the frequency
is set to 32, 44.1, 88.2, or 96 kHz, respectively. Therefore, the initial frequency is the same as the crystal
resonator, however, its error frequency is below 1% after reset.
When the analog PLL is still unlocked after at least ten rising-edges of the S/PDIF, a S/PDIF decoder can detect
the incoming S/PDIF signal. Thus, DOUT becomes low (MUTE) until the analog PLL locks. This MUTE period
is less than 1 ms (analog PLL
’
s lock-up time is less than 0.5 ms). When the decoder does not detect an incoming
S/PDIF signal, UNLOCK will output high level status at the LRCKO clock transition. SCKO keeps its frequency
at the latest tracked bit rate.
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參數(shù)描述 |
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| DIR1703E/2K | 制造商:Texas Instruments 功能描述:Audio Interface Receiver 28-Pin SSOP T/R 制造商:Texas Instruments 功能描述:AUD INTRFC RCVR 28SSOP - Tape and Reel |
| DIR-600/E | 制造商:D-Link Networks 功能描述: |
| DIR-605L/E | 制造商:D-Link Networks 功能描述: |
| DIR-615/E | 制造商:D-Link Networks 功能描述: |
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