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參數(shù)資料
| 型號(hào)： | DJIXEEAD0QE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁數(shù)： | 159/226頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXEEAD0QE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
161
4.13.3
Implementation Considerations
Before performing Cable Diagnostics, the twisted-pair to be tested may
be verified to be inactive.
All applicable link configurations should be attempted. Cable Diagnostic tests may be started if the
attempts indicate no link partners are active. If link partners are detected, additional tests and
decisions as to next steps may need to be implemented in the cable testing algorithm to ensure the
most accurate results.
Intel recommends that a 100BASE-TX link be attempted with MDI and MDIX enabled
sequentially, prior to performing Cable Diagnostic testing, to determine if a 100BASE-TX-only
link partner is present. If a link partner is in forced 100BASE-TX operation, transmitting MLT3,
the Cable Diagnostic test result will be undefined due to the interference MLT3 causes in
attempting to process the reflected Cable Diagnostic pulse. Auto MDI/MDIX on the link partner
should be accounted for in deriving the cable testing algorithm.
Intel recommends auto MDI/MDIX be disabled when running the cable tests. The transmit and
receive twisted-pairs must be tested one at a time with both short and long cable test suites. The
MDI/MDIX control bits in
Table 99, “Trim Enable Register (Address 27, Hex 1B)” on page 216
can be used to select the twisted-pair to be tested. This requirement creates a minimum of four test
permutations that must be completed to determine if the fault exists, the distance to the fault.
If Cable Diagnostics testing is completed using a powered down LXT9785 device as the link
partner, specific results can be expected. The results will indicate an open connection when the
PWRDWN hardware configuration pin is used. These power-down methods disable the internal
termination resistors to create a high impedance connection equivalent to an open circuit.
If Transmit Disable (Register bit 16.13) or software controlled Power-Down (Register bit 0.11) is
used, the powered down device transmit logic will look like an open circuit and the receive circuit
will look like a 100
terminated connection. The Transmit Disable bit and the software Power-
Down bit disable the transmit circuit but do not affect the receive circuit.
The result of Cable Diagnostic tests using an IP Phone indicate an open or a short fault at a gross
approximation of the distance to the IP Phone. The termination resistors are not powered and do
not create a proper termination. The filter circuit used by some manufacturers adversely affects the
test results.
Transmission and reception of packets is disabled when Cable Diagnostics is enabled. Internal
loopback must be disabled for Cable Diagnostics to operate properly. Internal loopback disables
the analog interface.
4.13.4
Basic Implementation
Register 29 is used to control and report the Cable Diagnostics test results. The function tests one
pair of the twisted-pair cable at a time. The basic process flow is described as follows (see
Table 100, “Cable Diagnostics Register (Address 29, Hex 1D)” on page 217
for Register 29 bit
definitions):
1. Disable auto-negotiation by clearing Register bit 0.12, set to MDI by clearing Register bits
27.9:8, and ensure internal loopback is disabled, Register bit 0.14 = 0.
2. Write 0x7400h to Register 29. Setting these bits places the device in short cable Cable
Diagnostics mode and forces link to drop. The device waits a specific amount of time (1.2 s to
1.5 s) to ensure link drops on any connected link partner, and initiates the Cable Diagnostics
test on the selected twisted-pair.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXEEAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXEEAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEEAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEECD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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