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| 型號(hào)： | DJIXEEED0SE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 90/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXEEED0SE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
92
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
D2
59
MDIX
I, ID, ST
MDIX Select
Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 27.8 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to
Table 40
“Intel LXT9785/LXT9785E MDIX Selection” on
page 119
.
When AMDIX_EN is active this pin is ignored.
When AMDIX_EN is inactive, all ports are forced to the
MDI or the MDIX function regardless of segmentation.
If this pin is active (high), MDI crossover (MDIX) is
selected. If this pin is inactive, non-crossover MDI
mode is set.
This pin is shared with RMII-RxER0. An external pull-
up resistor (see applications section for value) can be
used to set MDIX active while RxER0 is three-stated
during H/W reset. If no pull-up is used, the default
MDIX state is set inactive via the internal pull-down
resistor. Do not tie this pin directly to VCCIO (vs. using
a pull-up) in non-RMII modes.
L2,
L3,
M1
85
86
87
CFG_3
CFG_2
CFG_1
I, ST, ID
Global Port Configuration Defaults 1-3.
These pins are read at startup or reset. Their value at
that time is used to set the default state of register bits
shown in
Table 42 “Intel LXT9785/9785E Global
Hardware Configuration Settings” on page 129
for all
ports. These register bits can be read and overwritten
after startup / reset.
When operating in Hardware Control Mode, these pins
provide configuration control options for all the ports
(refer to
Table 42 “Intel LXT9785/9785E Global
Hardware Configuration Settings” on page 129
for
details).
M14
173
G_FX/TP
I, ST, ID
Global FX/TP Enable Default.
This pin is read at startup or reset. Its value at that time
is used to set the default state of Register bit 16.0 for
all ports. These register bits can be read and
overwritten after startup / reset. Refer to
Table 92 “Port
Configuration Register (Address 16, Hex 10)” on page 207
.
This input selects whether all the ports are defaulted to
TP vs. FX mode.
Table 32. Intel
LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 3 of 4)
Ball/Pin
Designation
Symbol
Type
1
Signal Description
2
BGA23
PQFP
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =
Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal
Pull-Down.
2. The IP/ID resistors are disabled during hardware power-down mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXELAD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELCD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXELAD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXELCD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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