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| 型號(hào)： | DJIXEPAD0QE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 153/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXEPAD0QE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
155
associated with message code #5 (Organizationally Unique Identifier (OUI) Tag Code). The
definition for the next pages to be sent out for this message code include some user-defined code
values. These values are loaded with randomly created data from an internal LSFR that is free
running and seeded with the PHY address of the LXT9785E port. The Next Pages are hard coded
in the logic (the LXT9785E ignores any data written into Register 7) and are outlined in
Table 47
.
The receiver monitors the next pages to determine that the exact next page data (especially the
random data) transmitted is received. As soon as the first non-matching next page is detected, the
DTE Discovery process is stopped and the base page is used to determine the capability options.
The Power-Enable Register bit 27.4 is set when a Remote-Power DTE is detected as the link
partner, and the last next page is repeatedly transmitted until software restarts the required
negotiation process (auto-negotiation or forced-speed mode).
The software should be written so that the negotiation is not restarted until the DTE has been
powered up over the Category 5 cable. The Power-Enable Register bit 27.4 is cleared upon
restarting or disabling auto-negotiation (selecting forced mode). The system must be able to detect
over-current conditions and be capable of disabling power in case the link partner is not a Remote-
Power DTE. Some examples of devices that would mistakenly set Power-Enable Register bit 27.4
are a token-ring balun and a loopback cable. Once link partner power has been stabilized and
sufficient time has passed for the link partner to initialize, the auto-negotiation process may be
restarted.
The negotiation process establishes link if a compatible mode exists between the LXT9785E and
the link partner. If a compatible mode does not exist (not compatible or not established within the
Link Fail Inhibit Timer period), the LXT9785E either restarts auto-negotiation/DTE discovery
(discovery is enabled (27.6=1) and auto-negotiation is enabled (0.12 = 1)), or normal negotiation
(discovery is disabled (27.6=0) and auto-negotiation is enabled (0.12 = 1)), or either 10 Mbps or
100 Mbps forced-mode operation (auto-negotiation is disabled (0.12 = 0)). The software must
detect this non-link state and disable power.
4.11.5
DTE Discovery Behavior
The device behavior checks the comparison bit after each next page is successfully auto-
negotiated. If the first next page or any subsequent next page does not match, the DTE Discovery
process transmits one last null page with the next page bit cleared to stop the DTE Discovery
Table 47. Next Page Message #5 Code Word Definitions
Next Page
Encoding
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OUI
Tagged
Message
1
a
1
0
t
0
0
0
0
0
0
0
0
1
0
1
User Page
1
1
a
0
0
t
3.10 3.11 3.12 3.13 3.14 3.15
2.0
2.1
2.2
2.3
2.4
User Page
2
1
a
0
0
t
2.5
2.6
2.7
2.8
2.9
2.10 2.11 2.12 2.13 2.14 2.15
User Page
3
1
a
0
0
t
0
0
L.8
L.7
L.6
L.5
L.4
L.3
L.2
L.1
L.0
User Page
4
1
a
0
0
t
L.10
L.9
L.8
L.7
L.6
L.5
L.4
L.3
L.2
L.1
L.0
1. a is the acknowledge bit; t is the toggle bit; L is the LFSR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXEPAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXEPAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXEPCD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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