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參數(shù)資料
| 型號(hào)： | DJIXPLAD0QE001 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| 中文描述： | 先進(jìn)的8端口10/100 Mbps的物理層收發(fā)器 |
| 文件頁(yè)數(shù)： | 152/226頁(yè) |
| 文件大?。?/td> | 1575K |
| 代理商： | DJIXPLAD0QE001 |
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
154
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
DTE DISCOVERY PROCESS ENABLE - Register Bit 27.6 (Dis_EN)
R/W Default value = 0: Disabled.
Register bit 27.6 controls the operation of the process. The discovery process is disabled when
Register bit 27.6 = 0, and enabled when Register bit 27.6 = 1. The MAC controller sets Register bit
27.6 to a 1 when a port search for a DTE requiring power is desired. Once set, Register bit 27.6
remains = 1 until the MAC clears it, either by directly clearing it or by resetting the PHY. This
allows the discovery process to continue to function if unsuccessful in detecting a DTE, without
being continually re-enabled by the MAC. If Register bit 27.6 is set after link is established, no
action is taken until after the link goes down.
POWER ENABLE - Register Bit 27.4 (Power_EN)
R Default value = 0: No Remote-Power DTE found.
Register bit 27.4 contains the result of the discovery process. When Register bit 27.4 = 0, the
discovery process has not found Remote-Power DTE, and when Register bit 27.4 = 1, the
discovery process has potentially found a DTE requiring power. This indicates power should be
applied to the Category 5 cable. Register bit 27.4 is polled by the MAC during the discovery
process, and is cleared when the PHY is reset, when auto-negotiation is restarted, or when auto-
negotiation is disabled. In the event of a discovery process being interrupted due to detection of an
already powered link partner (auto-negotiation completion or Parallel Detection), Register
bit 27.4 = 0.
STANDARD LINK PARTNER DETECTED - Register Bit 27.3 (SLP_Det)
R/W Clear on Read Default value = 0: No link partner found.
When Register bit 27.3 = 1, a standard link partner has been detected by the LXT9785E (NLPs,
MLT3 data, FLPs without next page support, or FLPs with non-matching next pages). This
indicates power should not be applied to the Category 5 cable. When Register bit 27.3 = 0, other
bits are checked to determine overall status of the link partner. Register bit 27.3 is cleared on read,
or DTE discovery is disabled, link is established, or auto-negotiation is either restarted or disabled.
LINK FAIL TIMEOUT - Register Bit 27.2 (LFIT Expired)
R/W Clear on Read Default value = 0 (Link Fail Inhibit timer has expired without establishment of
link with a standard link partner). Valid only when Standard Link Partner Detected Register bit
27.3 = 1.
Register bit 27.2 is set if link is not established prior to the Link Fail Inhibit Timer expiring. This
indicates that the Discovery process has restarted and the Standard Link Partner Detected Register
bit may no longer be valid. Register bit 27.2 is cleared on read, or DTE discovery is disabled, link
is established, or auto-negotiation is either restarted or disabled.
4.11.4
DTE Discovery Process Flow
The following section describes the DTE Discovery process.See
Figure 30, “Intel LXT9785E
Negotiation Flow Chart” on page 156
for a flow chart of the discovery process.When DTE
Discovery (27.6) and auto-negotiation (0.12) are enabled (auto-negotiation mode is required), the
LXT9785E transmits the auto-negotiation base page with the next page ability bit set (
“Auto-
Negotiation Advertisement Register (Address 4)” on page 204
).
System software polls Register 27 to determine if or when a Remote-Power DTE is detected. The
receiver monitors the line to determine if NLPs, MLT3 data, or FLP bursts are being received. If
the receive activity is FLP bursts, the status of the next page ability bit is checked. If the detected
“l(fā)ink partner” also supports next page, then the LXT9785E transmits out the next page sequence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DJIXPLAD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLAD0SE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLCD0QE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLCD0QE001 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLCD0SE000 | Advanced 8-Port 10/100 Mbps PHY Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DJIXPLAD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLAD0SE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLCD0QE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLCD0QE001 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| DJIXPLCD0SE000 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
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