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參數(shù)資料
| 型號： | DM4M32SJ6-15L |
| 英文描述： | Enhanced DRAM (EDRAM) Module |
| 中文描述： | 增強的DRAM（eDRAM內(nèi)存）模塊 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DM4M32SJ6-15L |
1-116
Switching Characteristics
Vcc = 5V + 5%, TA= 0 - 70oC, CL= 50pf
Note: These parameters do not include address and control buffer delays. See page 1-110 for derating factor.
Symbol
Description
t
AC
(1)
t
AC1
(1)
t
ASC
t
ASR
t
C
t
C1
t
CAE
t
CAH
t
CH
t
CQV
t
CRP
t
CWL
t
DH
t
DS
t
GQV
(1)
t
GQX
(2,3)
t
GQZ
(4,5)
Column Address Access Time for Addresses A
2-10
Column Address Setup Time
Row Enable Cycle Time
Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only
Row Address Setup Time
Column Address Latch Active Time
Column Address Hold Time
Column Address Latch High Time (Latch Transparent)
Column Address Latch High to Data Valid
Column Address Latch Inactive to Data Invalid for Addresses A
0-8
Column Address Latch Setup Time to Row Enable
/WE Low to /CAL Inactive
Data Input Hold Time
Data Input Setup Time
Output Enable Access Time
Output Enable to Output Drive Time
5
5
55
20
5
5
5
5
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
Units
12
5
0
15
0
5
t
AQX
t
AQX1
Column Address Change to Output Data Invalid for Addresses A
0-8
Column Address Change to Output Data Invalid for Addresses A
9 and
A
10
ns
5
t
ACH
Column Address Valid to /CAL Inactive (Write Cycle)
ns
12
t
CA
Address Cycle Time (Cache Hits)
ns
12
5
5
5
65
25
5
5
5
5
0
5
Min
Max
15
6
0
17
0
5
5
15
15
5
-12
-15
t
CQX
t
NRS
t
PC
t
RAC
(1)
t
RAC1
(1)
t
RAC2
(1,6)
t
RAH
Output Turn-Off Delay From Output Disabled (/G
↑
)
/CAL, /G, and /WE Setup Time For /RE-Only Refresh
Column Address Latch Cycle Time
Row Address Hold Time
Row Enable Access Time, On a Cache Miss
t
NRH
/CAL, /G, and /WE Hold Time For /RE-Only Refresh
t
MSU
/F and W/R Mode Select Setup Time
t
MH
/F and W/R Mode Select Hold Time
ns
0
5
0
5
ns
0
0
ns
5
5
ns
0
0
ns
5
5
ns
12
15
ns
30
35
ns
1.5
Row Enable Access Time for a Cache Write Hit
ns
30
35
1
t
CHR
/CAL Inactive Lead Time to /RE Inactive (Write Cycles Only)
-2
ns
-2
t
CHW
Column Address Latch High to Write Enable Low (Multiple Writes)
0
ns
0
Column Address Access Time for Addresses A
0
and A
1
ns
8
8
ns
1
1
Column Address Latch Inactive to Data Invalid for Addresses A
9
and A
10
1
ns
1
t
CQX1
Row Enable Access Time, On a Cache Hit (Limit Becomes t
AC
)
15
17
ns
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