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參數(shù)資料
| 型號(hào)： | DM4M32SJ6-15L |
| 英文描述： | Enhanced DRAM (EDRAM) Module |
| 中文描述： | 增強(qiáng)的DRAM（eDRAM內(nèi)存）模塊 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DM4M32SJ6-15L |
1-117
Switching Characteristics (continued)
Vcc = 5V + 5%, TA= 0 - 70oC, CL= 50pf
Note: These parameters do not include address and control buffer delays. See page 1-110 for derating factor.
Symbol
Description
t
RGX
t
RP
(7)
t
RP1
t
RP2
t
RRH
t
t
RSH
Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z
Row Precharge Time
Row Precharge Time, Cache Hit (Row=LRR) Read Cycle
Read Hold Time From Row Enable (Write Only)
Last Write Address Latch to End of Write
Row Enable to Column Address Latch Low For Second Write
9
20
8
0
ns
ns
ns
ns
ns
Min
Max
Units
35
25
t
RQX1
Row Enable High to Output Turn-On After Write Miss
ns
12
15
10
0
Row Precharge Time, Self-Refresh Mode
100
ns
100
Min
Max
10
40
-12
-15
12
15
RSW
ns
t
SC
Column Address Cycle Time
ns
12
15
t
SHR
t
SQV
(1)
t
SQX
(2,3)
t
SQZ
(4,5)
Select Hold From Row Enable
ns
0
0
Chip Select Access Time
ns
12
15
Output Turn-On From Select Low
ns
12
15
0
0
Output Turn-Off From Chip Select
ns
8
10
0
0
t
SSR
Select Setup Time to Row Enable
ns
5
5
t
T
Transition Time (Rise and Fall)
ns
10
10
1
1
t
WC
Write Enable Cycle Time
ns
12
15
t
WCH
Column Address Latch Low to Write Enable Inactive Time
ns
5
5
t
WI
Write Enable Inactive Time
ns
5
5
t
WP
t
WQV
(1)
t
WRP
Write Enable Active Time
Write Enable Setup Time to Row Enable
Write to Read Recovery (Cache Miss)
16
ns
ns
ns
5
Data Turn-Off From Write Enable Low
ns
t
WQX
(2,5)
t
WQZ
(3,4)
Data Output Turn-On From Write Enable High
ns
0
Data Valid From Write Enable High
ns
18
5
0
12
5
5
15
12
15
0
0
12
15
t
RE1
t
REF
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle
Refresh Period
ms
64
64
8
10
ns
t
WHR
Write Enable Hold After /RE
ns
0
0
t
RE
Row Enable Active Time
ns
30
100000
35
100000
t
RWL
Last Write Enable to End of Write
ns
12
15
t
WRR
(1) V
OUT
Timng Reference Point at 1.5V
(2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to V
OH
or V
OL
(3) MnimumSpecification is Referenced fromV
IH
and MaximumSpecification is Referenced fromV
IL
on Input Control Signal
(4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to V
OH
or V
OL
(5) MnimumSpecification is Referenced fromV
IL
and MaximumSpecification is Referenced fromV
IH
on Input Control Signal
(6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to t
RAC2
(7) For Back-to-Back /F Refreshes, t
RP
= 40ns. For Non-Consecutive /F Refreshes, t
RP
= 25ns and 32ns respectively.
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