參數(shù)資料
型號： DM562P
廠商： Electronic Theatre Controls, Inc.
英文描述： V.90 Intergrated Data/Fax/Voice/Speakephone Modem Device Single Chip with Memory Built in
中文描述： .90綜合數(shù)據(jù)/傳真/語音/ Speakephone調(diào)制解調(diào)器設(shè)備的單芯片，具有內(nèi)置的記憶
文件頁數(shù)： 37/43頁
文件大?。?/td> 292K
代理商： DM562P
DM562P
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
Preliminary
Version: DM562P-DS-P02
February 28, 2001
37
DM6580 Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
RXDCLK
V
DD
RXSCLK
RFS
DOR
DIR
DGND
SCLK
DOT
DIT
TFS
TXSCLK*2
TXDCLK
CLKIN
/RESET
EXTCLK
Vr
AVDDT
TXA2
TXA1
AGNDR
V
REFN
V
CM
V
REFP
AGNDT
RXIN
AVDDR
SPKR
I/O
O
P
O
I
O
I
P
O
O
I
I
O
O
I
I
I
O
I
O
O
P
O
O
O
P
I
I
O
Description
Receive Data Clock
Digital Power
Receive Sample Clock
Receive Frame Synchronization
Data Output For Receiver
Data Input For Receiver
Digital Ground
Serial Clock Synchronized With All Serial Data
Data Output For Transmitter
Data Input For Transmitter
Transmit Frame Synchronization
Transmit Sample Clock * 2
Transmit Data Clock
Master Clock Input (20.16MHz = 40.32MHz / 2 )
Codec Reset Input
External Transmit Data Clock
Internal Reference Voltage. Connect 0.1uF to DGND
Analog V
DD
For The Transmitter Analog Circuitry (+5V
DC
)
Transmit Negative Analog Output
Transmit Positive Analog Output
Analog Receiver Circuitry Signal Return Path
Negative Reference Voltage, V
CM
- 1V
Common Mode Voltage Output, 2.5V
Positive Reference Voltage, V
CM
+ 1V
Analog Transmitter Circuitry Signal Return Path
Receive Analog Input
Analog V
DD
For The Receiver Analog Circuitry (+5V
DC
)
Speaker Driver
DM6580 Functional Description
In this chip, we could roughly divide it into two major
parts: digital portion and analog portion. The
functional blocks are described separately in this
section. The analog circuits include a sigma-delta
modulator/demodulator, decimation/interpolation
filters, a speaker driver, low-pass filter and certain
logic circuits. The digital circuits is composed of Tx/Rx
clock generator/PLL, serial port, serial/parallel
conversions and control registers. All the clock
information the analog circuits need should be
provided by the digital clock system since the best
sampling instant of A/D and D/A depends on the
received signal and transmit signals. The data format
of A/D and D/A is 2's complement.
The master clock (FQ) is obtained from an external
signal connected to CLKIN. The different transmit and
receive clocks are obtained by master clock
frequency division in several programmable counters.
The Tx and Rx clocks can be synchronized on
external signals by performing the phase shifts in the
frequency division process. Two independent digital
phase locked loops are implemented using this
principle, one for transmit clock system, the other,
receive clock. The tracking of the transmit clock is
automatically done by the transmit DPLL circuit. The
receive DPLL circuit is controlled by the host
processor and it is actually an adjustable phase
shifter.
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