參數(shù)資料
型號(hào)： DM6381F
廠商： Electronic Theatre Controls, Inc.
英文描述： V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
中文描述： .34綜合數(shù)據(jù)/傳真/語音/揚(yáng)聲器調(diào)制解調(diào)器設(shè)備集
文件頁數(shù)： 10/40頁
文件大?。?/td> 341K
代理商： DM6381F
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
10
Final
Version: DM336P-DS-F02
August 15, 2000
c. Interrupt Identification Register (IIR): Address 2
Reset State 01h, Read only
bit7
bit6 bit5 bit4 bit3
FIFO
Enable
bit2
D2:
INTD1
bit1
D1:
INTD0
bit0
D0:
int
0
0
0
D3:
INTD2
Pending
In order to provide minimum software overhead
during data transfers, the virtual UART prioritizes
interrupts into four levels as followed: Receiver Line
Status (priority 1), Receiver Data Available (priority 2),
Character Timeout Indication (priority 2, FIFO mode
only), Transmitter Holding Register Empty (priority 3 ),
and Modem Status (priority 4).
The IIR register gives prioritized information as to the
status of interrupt conditions. When accessed, the IIR
indicates the highest priority interrupt that is pending,
as indicated by bits INTD(2-0).
Bit 0: This bit can be used in either a prioritized
interrupt or polled environment to indicate
whether an interrupt is pending. When this bit is
a logic 0, an interrupt is pending, and the IIR
contents may be used as a pointer to the
appropriate interrupt service routine. When bit 0
is a logic 1, no interrupt is pending, and polling
(if used) continues.
Bit 1-2: These two bits of the IIR are used to identify
the highest priority interrupt pending, as
indicated in the table below.
Bit 3: In character mode, this bit is 0. In FIFO mode,
this bit is set, along with bit 2, when a timeout
interrupt is pending.
Bit 4-6: Not used
Bit 7: This bit is set when FCR0 = 1.
D3
0
0
D2
0
1
D1
0
1
D0 Priority Level
1
0
Highest
Interrupt Type
-
Receiver Line
Status
Condition
-
Reset
-
-
Overrun Error, Parity
Error, Framing Error or
Break Interrupt
Receiver Data Available
or Trigger Level Reached
Reads the Line Status
Register
0
1
0
0
Second
Receiver Data
Available
Reads the Receiver
Buffer Register or the
FIFO Drops Below The
Threshold Value
Reads The Receiver
Buffer Register
1
1
0
0
Second
Character
Timeout
Indication
No characters have been
read from or written to the
Rx FIFO during
programming time
interval, and the Rx FIFO
is not empty
Transmitter Holding
Register Empty
0
0
1
0
Third
Transmitter
Holding Register
Empty
Reads the IIR Register or
(if source of interrupt)
Writes To The Transmitter
Holding Register
Reads the Modem Status
Register
0
0
0
0
Fourth
Modem Status
Clear to Send, Data Set
Ready, Ring Indicator or
Data Carrier Detected
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