參數(shù)資料
型號(hào)： DM6383F
廠商： Electronic Theatre Controls, Inc.
英文描述： V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
中文描述： .34綜合數(shù)據(jù)/傳真/語音/揚(yáng)聲器調(diào)制解調(diào)器設(shè)備集
文件頁數(shù)： 22/40頁
文件大?。?/td> 341K
代理商： DM6383F
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
22
Final
Version: DM336P-DS-F02
August 15, 2000
Chip 2: DM6381/DM6382 ITU-T V.34 TX and RX Digital Signal Processor (TX DSP and
RX DSP) Description
DM6381/82 Description
The DM6381/DM6382 are application specific Digital
Signal Processors (DSP) dedicated to V.34 modem
operation. They are used in pairs. The primary
component of these devices is a 22.43Mips DSP core
processor. The basic clock frequency of this device is
40.32MHz. An internal built PLL circuit is used to
boost the clock from 40.32MHz to 80.64MHz or
89.74MHz. This 80.64MHz/89.74MHz clock is used
as the clock source of DSP core processor. A 16-byte
dual port SRAM is utilized to provide the
communication between DSP and the DM6383.
There are two dedicated serial ports that provide the
link between the DSP and the DM6380. The
DM6381/DM6382 are bonded-out in a 100-pin QFP
package for mass production, and provide the most
economical package.
DM6381/82 Block Diagram
Timing
Logical & PLL
Serial Port
Dual Port
RAM
ROM
DSP Core
Data
RAM
Program
RAM
OSCI
OSCO
MSCLK
CODEC_CLK
PMA[0:13]
PMD[0:23]
DMA[0:13]
DMD[0:15]
DM6381/82 Features
DM6381 for TX data-pump, DM6382 for RX data-
pump
Build in program ROM
2 serial ports to interface with codec
16 byte dual port RAM
Clock Generator for codec chip and controller chip
Build in PLL
相關(guān)PDF資料
PDF描述
DM336P V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
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