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參數(shù)資料
| 型號： | DM6383F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set |
| 中文描述： | .34綜合數(shù)據(jù)/傳真/語音/揚聲器調制解調器設備集 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大?。?/td> | 341K |
| 代理商： | DM6383F |
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DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Final
Version: DM336P-DS-F02
August 15, 2000
25
DM6381/82 Pin Description
(continued)
Pin No.
69
73
74
75
76
91 - 92
Pin Name
/RESET
/IRQ0
/IRQ1
/IRQ2
/IRQ3
TEST, TEST1
I/O
I
I
I
I
I
I
Description
Reset Pin Of DSP Chip
, low active.
Interrupt 0 Input
Interrupt 1 Input
Interrupt 2 Input
Interrupt 3 Input
These three pins define the testing mode operation of
DM6381/DM6382 as followed:
When Test=0
Test1
0, PLL output clock is 89.74MHz.
1, PLL output clock is 80.64MHz.
When Test=1:
Reserved for mass production testing mode.
All these 2 pins are pulled low internally.
Frame Signal Of Serial Port 1
Data Output Pin Of Serial Port 1
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP1 signal.
Data Input Pin Of The Serial Port 1
The serial data is sampled at the falling edge of the SCLK. The MSB is
coming immediately after the falling of FR_SP1 signal.
Reference Clock For Serial Port 1 And Serial Port 2
Data Output Pin Of Serial Port 2
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP2 signal.
96
97
FR_SP1
TD_SP1
I/O
O
98
RD_SP1
I
99
100
SCLK
TD_SP2
I
O
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