參數(shù)資料
型號: DM7473
廠商: Fairchild Semiconductor Corporation
英文描述: Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs(雙J-K主從觸發(fā)器(帶清除端和互補(bǔ)輸出))
中文描述: 雙主從JK觸發(fā)器明確和互補(bǔ)輸出(雙JK主從觸發(fā)器(帶清除端和互補(bǔ)輸出))
文件頁數(shù): 1/3頁
文件大小: 39K
代理商: DM7473
2000 Fairchild Semiconductor Corporation
DS006525
www.fairchildsemi.com
September 1986
Revised February 2000
D
DM7473
Dual Master-Slave J-K Flip-Flops
with Clear and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flops after a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave. The logic states of the J and K
inputs must not be allowed to change while the clock is
HIGH. Data transfers to the outputs on the falling edge of
the clock pulse. A LOW logic level on the clear input will
reset the outputs regardless of the logic states of the other
inputs.
Ordering Code:
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
=
Positive pulse data. the J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q
0
=
The output logic level before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each HIGH level clock pulse.
Order Number
DM7473N
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
CLR
L
H
H
H
H
CLK
X
J
X
L
H
L
H
K
X
L
L
H
H
Q
L
Q
0
H
L
Q
H
Q
0
L
H
Toggle
相關(guān)PDF資料
PDF描述
DM7473N Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs(雙正邊緣觸發(fā)的D觸發(fā)器(帶預(yù)置、清除端和互補(bǔ)輸出))
DM7474M Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs
DM7474N Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs
DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs(雙主從J-K觸發(fā)器(帶預(yù)置、清除端和互補(bǔ)輸出))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM7473J/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop
DM7473N 功能描述:觸發(fā)器 Dl JK M/S Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel
DM7473N/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop
DM7473N/B+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop
DM7474 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs