參數(shù)資料
型號(hào): DM74ALS646WM
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Octal 3-STATE Bus Transceiver and Register
中文描述: ALS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: 0.300 INCH, MS-013, SOIC-24
文件頁(yè)數(shù): 4/6頁(yè)
文件大小: 56K
代理商: DM74ALS646WM
www.fairchildsemi.com
4
D
Switching Characteristics
over recommended operating free air temperature range
Note 5:
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol
Parameter
Conditions
From (Input)
To (Output)
CBA or CAB
to A or B
CBA or CAB
Min
Max
Units
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
V
CC
=
4.5V to 5.5V,
C
L
=
50 pF,
R
1
=
R
2
=
500
,
T
A
=
Min to Max
10
30
ns
t
PHL
5
17
ns
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
to A or B
A or B to
B or A
t
PLH
5
20
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
A or B to
B or A
SBA or SAB
3
12
ns
t
PLH
LOW-to-HIGH Level Output
(with A or B LOW) (Note 5)
Propagation Delay Time
to A or B
12
35
ns
t
PHL
SBA or SAB
HIGH-to-LOW Level Output
(with A or B LOW) (Note 5)
Propagation Delay Time
to A or B
5
20
ns
t
PLH
SBA or SAB
LOW-to-HIGH Level Output
(with A or B HIGH) (Note 5)
Propagation Delay Time
to A or B
6
25
ns
t
PHL
SBA or SAB
HIGH-to-LOW Level Output
(with A or B HIGH) (Note 5)
to A or B
5
20
ns
t
PZH
Output Enable Time
G to
A or B
3
17
ns
to HIGH Level Output
t
PZL
Output Enable Time
G to
5
20
ns
to LOW Level Output
A or B
t
PHZ
Output Disable Time
G to
A or B
1
10
ns
from HIGH Level Output
t
PLZ
Output Disable Time
G to
2
16
ns
from LOW Level Output
Output Enable Time
to HIGH Level Output
A or B
DIR to
A or B
t
PZH
6
30
ns
t
PZL
Output Enable Time
to LOW Level Output
Output Disable Time
DIR to
A or B
DIR to
5
25
ns
t
PHZ
1
10
ns
from HIGH Level Output
Output Disable Time
from LOW Level Output
A or B
DIR to
A or B
t
PLZ
2
16
ns
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