參數(shù)資料
型號: DM74ALS652-01
廠商: Fairchild Semiconductor Corporation
英文描述: Octal 3-STATE Bus Transceiver and Register
中文描述: 八路三態(tài)總線收發(fā)器和注冊
文件頁數(shù): 4/6頁
文件大小: 70K
代理商: DM74ALS652-01
www.fairchildsemi.com
4
D
Switching Characteristics
over recommended operating free air temperature range
(Note 6)
Note 6:
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol
Parameter
Conditions
From (Input)
To (Output)
CBA or CAB
to A or B
Min
Max
Units
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
V
CC
=
4.5V to 5.5V,
C
L
=
50 pF,
R
1
=
R
2
=
500
,
T
A
=
Min to Max
10
30
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
CBA or CAB
to A or B
A or B to
5
17
ns
t
PLH
5
18
ns
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
B or A
A or B to
B or A
t
PHL
3
12
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
(with A or B LOW) (Note 6)
SBA or SAB
to A or B
12
35
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
(with A or B LOW) (Note 6)
SBA or SAB
to A or B
6
20
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
(with A or B HIGH) (Note 6)
SBA or SAB
to A or B
6
25
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
(with A or B HIGH) (Note 6)
SBA or SAB
to A or B
5
20
ns
t
PZH
Output Enable Time
GBA to
3
17
ns
to HIGH Level Output
A
t
PZL
Output Enable Time
to LOW Level Output
GBA to
A
5
18
ns
t
PHZ
Output Disable Time
GBA to
1
10
ns
from HIGH Level Output
A
t
PLZ
Output Disable Time
from LOW Level Output
Output Enable Time
GBA to
A
GAB to
2
16
ns
t
PZH
6
22
ns
to HIGH Level Output
Output Enable Time
to LOW Level Output
B
t
PZL
GAB to
B
6
18
ns
t
PHZ
Output Disable Time
from HIGH Level Output
Output Disable Time
GAB to
B
GAB to
1
10
ns
t
PLZ
2
16
ns
from LOW Level Output
B
相關PDF資料
PDF描述
DM74ALS652 Octal 3-STATE Bus Transceiver and Register(八總線收發(fā)器和寄存器(三態(tài)輸出))
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