參數(shù)資料
型號: DM74ALS652WM
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Octal 3-STATE Bus Transceiver and Register
中文描述: ALS SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: 0.300 INCH, MS-013, SOIC-24
文件頁數(shù): 4/6頁
文件大?。?/td> 57K
代理商: DM74ALS652WM
www.fairchildsemi.com
4
D
Switching Characteristics
over recommended operating free air temperature range
(Note 6)
Note 6:
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol
Parameter
Conditions
From (Input)
To (Output)
CBA or CAB
to A or B
Min
Max
Units
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
V
CC
=
4.5V to 5.5V,
C
L
=
50 pF,
R
1
=
R
2
=
500
,
T
A
=
Min to Max
10
30
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
CBA or CAB
to A or B
A or B to
5
17
ns
t
PLH
5
18
ns
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
B or A
A or B to
B or A
t
PHL
3
12
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
(with A or B LOW) (Note 6)
SBA or SAB
to A or B
12
35
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
(with A or B LOW) (Note 6)
SBA or SAB
to A or B
6
20
ns
t
PLH
Propagation Delay Time
LOW-to-HIGH Level Output
(with A or B HIGH) (Note 6)
SBA or SAB
to A or B
6
25
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
(with A or B HIGH) (Note 6)
SBA or SAB
to A or B
5
20
ns
t
PZH
Output Enable Time
to HIGH Level Output
GBA to
A
3
17
ns
t
PZL
Output Enable Time
to LOW Level Output
GBA to
A
5
18
ns
t
PHZ
Output Disable Time
GBA to
1
10
ns
from HIGH Level Output
A
t
PLZ
Output Disable Time
GBA to
2
16
ns
from LOW Level Output
Output Enable Time
to HIGH Level Output
A
t
PZH
GAB to
B
6
22
ns
t
PZL
Output Enable Time
to LOW Level Output
Output Disable Time
GAB to
B
GAB to
6
18
ns
t
PHZ
1
10
ns
from HIGH Level Output
Output Disable Time
from LOW Level Output
B
t
PLZ
GAB to
B
2
16
ns
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