參數(shù)資料
型號: DM74ALS74ASJX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Dual D-Type Flip-Flop
中文描述: ALS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝: 5.30 MM, EIAJ TYPE2, SOP-14
文件頁數(shù): 4/7頁
文件大?。?/td> 68K
代理商: DM74ALS74ASJX
www.fairchildsemi.com
4
D
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
°
C.
Symbol
Parameter
Conditions
Note 4:
I
CC
is measured with D, CLK and PRESET grounded, then with D, CLK and CLEAR grounded.
Note 5:
I
IL
PRE and CLR pins not guaranteed to meet specifications with both PRE and CLK LOW.
Switching Characteristics
over recommended operating free air temperature range.
Parameter
Conditions
Min
Typ
Max
Units
V
IK
V
OH
Input Clamp Voltage
V
CC
=
4.5V, I
I
=
18 mA
I
OH
=
0.4 mA
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V
V
IH
=
2V
V
CC
=
5.5V,
V
IH
=
7V
V
CC
=
5.5V,
V
IH
=
2.7V
V
CC
=
5.5V,
V
IL
=
0.4V
V
CC
=
5.5V, V
O
=
2.25V
V
CC
=
5.5V (Note 4)
1.5
V
HIGH Level
Output Voltage
LOW Level
V
CC
2
V
V
OL
I
OL
=
8 mA
0.35
0.5
V
Output Voltage
Input Current @
Max Input Voltage
I
I
Clock, D
Preset, Clear
0.1
0.2
mA
I
IH
HIGH Level
Input Current
Clock, D
Preset, Clear
20
40
0.2
0.4
112
4
μ
A
I
IL
LOW Level
Input Current
Output Drive Current
Clock, D
Preset, Clear (Note 5)
mA
I
O
I
CC
30
mA
Supply Current
2.4
mA
From
To
Min
Max
Units
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
V
CC
=
4.5V to 5.5V
R
L
=
500
C
L
=
50 pF
34
MHz
Preset or Clear
Q or Q
3
5
13
15
ns
ns
Clock
Q or Q
5
5
16
18
ns
ns
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