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參數(shù)資料
| 型號： | DM74LS47MX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Decoder/Driver |
| 中文描述： | LS SERIES, SEVEN SEGMENT DECODER/DRIVER, INVERTED OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 67K |
| 代理商： | DM74LS47MX |
www.fairchildsemi.com
2
D
Truth Table
Note 2:
BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a HIGH
level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking or a decimal 0 is not
desired. X
=
input may be HIGH or LOW.
Note 3:
When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a HIGH level regardless of the state of any other input
condition.
Note 4:
When ripple-blanking input (RBI) and inputs A0, A1, A2 and A3 are LOW level, with the lamp test input at HIGH level, all segment outputs go to a
HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition).
Note 5:
When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held at a HIGH level, and a LOW level is applied to lamp test input, all segment
outputs go to a LOW level.
Functional Description
The DM74LS47 decodes the input data in the pattern indi-
cated in the Truth Table and the segment identification
illustration. If the input data is decimal zero, a LOW signal
applied to the RBI blanks the display and causes a multi-
digit display. For example, by grounding the RBI of the
highest order decoder and connecting its BI/RBO to RBI of
the next lowest order decoder, etc., leading zeros will be
suppressed. Similarly, by grounding RBI of the lowest order
decoder and connecting its BI/RBO to RBI of the next high-
est order decoder, etc., trailing zeros will be suppressed.
Leading and trailing zeros can be suppressed simulta-
neously by using external gates, i.e.: by driving RBI of a
intermediate decoder from an OR gate whose inputs are
BI/RBO of the next highest and lowest order decoders. BI/
RBO also serves as an unconditional blanking input. The
internal NAND gate that generates the RBO signal has a
resistive pull-up, as opposed to a totem pole, and thus BI/
RBO can be forced LOW by external means, using wired-
collector logic. A LOW signal thus applied to BI/RBO turns
off all segment outputs. This blanking feature can be used
to control display intensity by varying the duty cycle of the
blanking signal. A LOW signal applied to LT turns on all
segment outputs, provided that BI/RBO is not forced LOW.
Decimal
or
Inputs
Outputs
Note
Function
0
1
2
3
LT
H
H
H
H
RBI
H
X
X
X
A3
L
L
L
L
A2
L
L
L
L
A1
L
L
H
H
A0
L
H
L
H
BI/RBO
H
H
H
H
a
L
H
L
L
b
L
L
L
L
c
L
L
H
L
d
L
H
L
L
e
L
H
L
H
f
L
H
H
H
g
H
H
L
L
(Note 2)
(Note 2)
4
5
6
7
8
H
H
H
H
H
X
X
X
X
X
L
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
L
H
L
L
L
H
H
L
L
L
L
L
L
L
H
L
L
H
L
H
H
L
H
L
L
L
L
H
L
L
L
L
H
L
9
10
11
12
13
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
L
L
L
H
H
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
L
L
H
L
H
L
H
H
H
L
H
H
L
L
L
L
L
L
L
14
15
BI
RBI
LT
H
H
X
H
L
X
X
X
L
X
H
H
X
L
X
H
H
X
L
X
H
H
X
L
X
L
H
X
L
X
H
H
L
L
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
L
H
H
H
L
(Note 3)
(Note 4)
(Note 5)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM74LS533N | Octal Transparent Latch with 3-STATE Outputs |
| DM74LS533 | Octal Transparent Latch with 3-STATE Outputs |
| DM74LS533WMX | 8-Bit D-Type Latch |
| DM74LS533WM | Octal Transparent Latch with 3-STATE Outputs |
| DM74LS534 | Octal D-Type Flip-Flop with 3-STATE Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM74LS47N | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 BCD to 7-Seg Dec/Drv RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| DM74LS503N | 功能描述:寄存器 8-Bit Succ App Reg RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| DM74LS51 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DM74LS51M | 功能描述:邏輯門 8-Bit Succ App Reg RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| DM74LS51MX | 功能描述:邏輯門 8-Bit Succ App Reg RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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